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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2012-11-15 20:56:03 +0000 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2012-11-15 20:56:03 +0000 |
| commit | bdface56995a87b1f48b5a0ede996d604e46fab4 (patch) | |
| tree | a99625bf0a8832db7e03586586a00e4ac52aa8f7 /llvm/lib | |
| parent | d9cb0ba66086c0ec826bb5e06b1850e49ca0f000 (diff) | |
| download | bcm5719-llvm-bdface56995a87b1f48b5a0ede996d604e46fab4.tar.gz bcm5719-llvm-bdface56995a87b1f48b5a0ede996d604e46fab4.zip | |
PowerPC: Lowering floor intrinsic for Altivec
This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and
llvm.nearbyint to Altivec instruction when using 4 single-precision
float vectors.
llvm-svn: 168086
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 10 |
2 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index d51baa6a576..7d97450676e 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -402,6 +402,10 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); + setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); + setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); + setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); + setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index ba58c3e4ac8..87758e90fbd 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -721,3 +721,13 @@ def : Pat<(v4f32 (sint_to_fp (v4i32 VRRC:$vA))), (VCFSX_0 VRRC:$vA)>; def : Pat<(v4f32 (uint_to_fp (v4i32 VRRC:$vA))), (VCFUX_0 VRRC:$vA)>; + +// Floating-point rounding +def : Pat<(v4f32 (ffloor (v4f32 VRRC:$vA))), + (VRFIM VRRC:$vA)>; +def : Pat<(v4f32 (fceil (v4f32 VRRC:$vA))), + (VRFIP VRRC:$vA)>; +def : Pat<(v4f32 (ftrunc (v4f32 VRRC:$vA))), + (VRFIZ VRRC:$vA)>; +def : Pat<(v4f32 (fnearbyint (v4f32 VRRC:$vA))), + (VRFIN VRRC:$vA)>; |
