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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-10-04 13:12:08 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-10-04 13:12:08 +0000 |
| commit | bd5d2f028411ca98ebac844cf0114836b8fc1186 (patch) | |
| tree | 600b6601897dc0fadb819e6ef45f40f92d6705e2 /llvm/lib | |
| parent | 482d3f41e5dc909c2e386075042a03256b0d88c8 (diff) | |
| download | bcm5719-llvm-bd5d2f028411ca98ebac844cf0114836b8fc1186.tar.gz bcm5719-llvm-bd5d2f028411ca98ebac844cf0114836b8fc1186.zip | |
[X86][SSE] Add support for lowering unary shuffles to PACKSS/PACKUS
Extension to D38472
llvm-svn: 314901
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 36 |
1 files changed, 24 insertions, 12 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a6cd747999c..08c944ca696 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -8683,24 +8683,36 @@ static SDValue lowerVectorShuffleWithPACK(const SDLoc &DL, MVT VT, MVT PackSVT = MVT::getIntegerVT(BitSize * 2); MVT PackVT = MVT::getVectorVT(PackSVT, NumElts / 2); - // TODO - Add support for unary packs. - SmallVector<int, 32> BinaryMask; - createPackShuffleMask(VT, BinaryMask, false); - - if (isShuffleEquivalent(V1, V2, Mask, BinaryMask)) { - SDValue VV1 = DAG.getBitcast(PackVT, V1); - SDValue VV2 = DAG.getBitcast(PackVT, V2); - if ((V1.isUndef() || DAG.ComputeNumSignBits(VV1) > BitSize) && - (V2.isUndef() || DAG.ComputeNumSignBits(VV2) > BitSize)) + auto LowerWithPACK = [&](SDValue N1, SDValue N2) { + SDValue VV1 = DAG.getBitcast(PackVT, N1); + SDValue VV2 = DAG.getBitcast(PackVT, N2); + if ((N1.isUndef() || DAG.ComputeNumSignBits(VV1) > BitSize) && + (N2.isUndef() || DAG.ComputeNumSignBits(VV2) > BitSize)) return DAG.getNode(X86ISD::PACKSS, DL, VT, VV1, VV2); if (Subtarget.hasSSE41() || PackSVT == MVT::i16) { APInt ZeroMask = APInt::getHighBitsSet(BitSize * 2, BitSize); - if ((V1.isUndef() || DAG.MaskedValueIsZero(VV1, ZeroMask)) && - (V2.isUndef() || DAG.MaskedValueIsZero(VV2, ZeroMask))) + if ((N1.isUndef() || DAG.MaskedValueIsZero(VV1, ZeroMask)) && + (N2.isUndef() || DAG.MaskedValueIsZero(VV2, ZeroMask))) return DAG.getNode(X86ISD::PACKUS, DL, VT, VV1, VV2); } - } + + return SDValue(); + }; + + // Try binary shuffle. + SmallVector<int, 32> BinaryMask; + createPackShuffleMask(VT, BinaryMask, false); + if (isShuffleEquivalent(V1, V2, Mask, BinaryMask)) + if (SDValue Pack = LowerWithPACK(V1, V2)) + return Pack; + + // Try unary shuffle. + SmallVector<int, 32> UnaryMask; + createPackShuffleMask(VT, UnaryMask, true); + if (isShuffleEquivalent(V1, V2, Mask, UnaryMask)) + if (SDValue Pack = LowerWithPACK(V1, V1)) + return Pack; return SDValue(); } |

