diff options
| author | Nate Begeman <natebegeman@mac.com> | 2008-02-12 22:54:40 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2008-02-12 22:54:40 +0000 |
| commit | bcc182f50d8a6067d541d744b4f033d3891d5374 (patch) | |
| tree | 8f72677439ce8a370593205ad56334f500afd4ba /llvm/lib | |
| parent | 8ef50214f023a4e334542c49207e56a1662cf65f (diff) | |
| download | bcm5719-llvm-bcc182f50d8a6067d541d744b4f033d3891d5374.tar.gz bcm5719-llvm-bcc182f50d8a6067d541d744b4f033d3891d5374.zip | |
Remove some dead code
llvm-svn: 47036
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 8176f24ef3d..301f361295a 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -910,8 +910,8 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, } static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, - unsigned *vRegs, unsigned ArgNo, - unsigned &NumGPRs, unsigned &ArgOffset) { + unsigned ArgNo, unsigned &NumGPRs, + unsigned &ArgOffset) { MachineFunction &MF = DAG.getMachineFunction(); MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); SDOperand Root = Op.getOperand(0); @@ -936,19 +936,16 @@ static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, if (ObjGPRs == 1) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - vRegs[NumGPRs] = VReg; ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); if (ObjectVT == MVT::f32) ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); } else if (ObjGPRs == 2) { unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); - vRegs[NumGPRs] = VReg; ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); - vRegs[NumGPRs+1] = VReg; SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); @@ -987,11 +984,10 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { SDOperand Root = Op.getOperand(0); unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot unsigned NumGPRs = 0; // GPRs used for parameter passing. - unsigned VRegs[4]; unsigned NumArgs = Op.Val->getNumValues()-1; for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) - ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo, + ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo, NumGPRs, ArgOffset)); bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; |
