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authorCraig Topper <craig.topper@intel.com>2017-09-03 17:52:19 +0000
committerCraig Topper <craig.topper@intel.com>2017-09-03 17:52:19 +0000
commitbb6506d251b52df06546f3a838f34309d1f9b17e (patch)
tree04890396402181bbb120e2e5aa15cb45e4a0d78d /llvm/lib
parentc9fac9e15117a2dbfafc290ad155a3bea65e5faf (diff)
downloadbcm5719-llvm-bb6506d251b52df06546f3a838f34309d1f9b17e.tar.gz
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[X86] Canonicalize (concat_vectors X, zero) -> (insert_subvector zero, X, 0).
In a future patch, I plan to teach isel to use a small vector move with implicit zeroing of the upper elements when it sees the (insert_subvector zero, X, 0) pattern. llvm-svn: 312448
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp10
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e0c17a2c27f..0193f2bfd58 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -35728,6 +35728,16 @@ static SDValue combineInsertSubvector(SDNode *N, SelectionDAG &DAG,
return DAG.getNode(X86ISD::SUBV_BROADCAST, dl, OpVT,
SubVec.getOperand(0));
}
+
+ // If we're inserting all zeros into the upper half, change this to
+ // an insert into an all zeros vector. We will match this to a move
+ // with implicit upper bit zeroing during isel.
+ if (ISD::isBuildVectorAllZeros(SubVec.getNode())) {
+ return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT,
+ getZeroVector(OpVT, Subtarget, DAG, dl), SubVec2,
+ Vec.getOperand(2));
+
+ }
}
}
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