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| author | Ayman Musa <ayman.musa@intel.com> | 2017-02-15 08:12:16 +0000 |
|---|---|---|
| committer | Ayman Musa <ayman.musa@intel.com> | 2017-02-15 08:12:16 +0000 |
| commit | b8a4f255dd63ed1ed6a1b4a0f8228f86e0db991c (patch) | |
| tree | 1c2d2cf4517841fa17d8528623c605a0b87ae670 /llvm/lib | |
| parent | 32ac5e41ef957ed8ac497ebfbf84b61ee95be9a2 (diff) | |
| download | bcm5719-llvm-b8a4f255dd63ed1ed6a1b4a0f8228f86e0db991c.tar.gz bcm5719-llvm-b8a4f255dd63ed1ed6a1b4a0f8228f86e0db991c.zip | |
[X86][AVX] Remove REX_W from AVX instructions.
There is no meaning for REX_W in VEX encoded AVX instruction.
Differential Revision: https://reviews.llvm.org/D29894
llvm-svn: 295157
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrSSE.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index a807311ed86..d2dfb1b5d7d 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -6071,20 +6071,20 @@ multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> { "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set GR64:$dst, (extractelt (v2i64 VR128:$src1), imm:$src2))]>, - Sched<[WriteShuffle]>, REX_W; + Sched<[WriteShuffle]>; let SchedRW = [WriteShuffleLd, WriteRMW] in def mr : SS4AIi8<opc, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src1, u8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(store (extractelt (v2i64 VR128:$src1), imm:$src2), - addr:$dst)]>, REX_W; + addr:$dst)]>; } let Predicates = [HasAVX, NoDQI] in defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W; -defm PEXTRQ : SS41I_extract64<0x16, "pextrq">; +defm PEXTRQ : SS41I_extract64<0x16, "pextrq">, REX_W; /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory /// destination |
