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authorDylan Noblesmith <nobled@dreamwidth.org>2014-08-25 01:59:38 +0000
committerDylan Noblesmith <nobled@dreamwidth.org>2014-08-25 01:59:38 +0000
commitb899464f5ba0b71623611303112c323ad2f2a6c0 (patch)
tree437069272b9afd76c758c9fb300832252160e521 /llvm/lib
parent6076debd98fef002b4f0147980c39114b8a0fef0 (diff)
downloadbcm5719-llvm-b899464f5ba0b71623611303112c323ad2f2a6c0.tar.gz
bcm5719-llvm-b899464f5ba0b71623611303112c323ad2f2a6c0.zip
AArch64: unique_ptr-ify map structures
llvm-svn: 216366
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AArch64/AArch64CollectLOH.cpp35
1 files changed, 9 insertions, 26 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
index 38dbeb95927..bb57d76a8cd 100644
--- a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
+++ b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
@@ -195,12 +195,14 @@ typedef SetVector<const MachineInstr *> SetOfMachineInstr;
/// Map a basic block to a set of instructions per register.
/// This is used to represent the exposed uses of a basic block
/// per register.
-typedef MapVector<const MachineBasicBlock *, SetOfMachineInstr *>
+typedef MapVector<const MachineBasicBlock *,
+ std::unique_ptr<SetOfMachineInstr[]>>
BlockToSetOfInstrsPerColor;
/// Map a basic block to an instruction per register.
/// This is used to represent the live-out definitions of a basic block
/// per register.
-typedef MapVector<const MachineBasicBlock *, const MachineInstr **>
+typedef MapVector<const MachineBasicBlock *,
+ std::unique_ptr<const MachineInstr *[]>>
BlockToInstrPerColor;
/// Map an instruction to a set of instructions. Used to represent the
/// mapping def to reachable uses or use to definitions.
@@ -237,9 +239,9 @@ static SetOfMachineInstr &getSet(BlockToSetOfInstrsPerColor &sets,
SetOfMachineInstr *result;
BlockToSetOfInstrsPerColor::iterator it = sets.find(&MBB);
if (it != sets.end())
- result = it->second;
+ result = it->second.get();
else
- result = sets[&MBB] = new SetOfMachineInstr[nbRegs];
+ result = (sets[&MBB] = make_unique<SetOfMachineInstr[]>(nbRegs)).get();
return result[reg];
}
@@ -289,9 +291,9 @@ static void initReachingDef(MachineFunction &MF,
unsigned NbReg = RegToId.size();
for (MachineBasicBlock &MBB : MF) {
- const MachineInstr **&BBGen = Gen[&MBB];
- BBGen = new const MachineInstr *[NbReg];
- memset(BBGen, 0, sizeof(const MachineInstr *) * NbReg);
+ auto &BBGen = Gen[&MBB];
+ BBGen = make_unique<const MachineInstr *[]>(NbReg);
+ memset(BBGen.get(), 0, sizeof(const MachineInstr *) * NbReg);
BitVector &BBKillSet = Kill[&MBB];
BBKillSet.resize(NbReg);
@@ -422,22 +424,6 @@ static void reachingDefAlgorithm(MachineFunction &MF,
} while (HasChanged);
}
-/// Release all memory dynamically allocated during the reaching
-/// definition algorithm.
-static void finitReachingDef(BlockToSetOfInstrsPerColor &In,
- BlockToSetOfInstrsPerColor &Out,
- BlockToInstrPerColor &Gen,
- BlockToSetOfInstrsPerColor &ReachableUses) {
- for (auto &IT : Out)
- delete[] IT.second;
- for (auto &IT : In)
- delete[] IT.second;
- for (auto &IT : ReachableUses)
- delete[] IT.second;
- for (auto &IT : Gen)
- delete[] IT.second;
-}
-
/// Reaching definition algorithm.
/// \param MF function on which the algorithm will operate.
/// \param[out] ColorOpToReachedUses will contain the result of the reaching
@@ -474,9 +460,6 @@ static void reachingDef(MachineFunction &MF,
if (!DummyOp)
reachingDefAlgorithm(MF, ColorOpToReachedUses, In, Out, Gen, Kill,
ReachableUses, RegToId.size());
-
- // finit.
- finitReachingDef(In, Out, Gen, ReachableUses);
}
#ifndef NDEBUG
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