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| author | Craig Topper <craig.topper@intel.com> | 2019-02-04 04:44:20 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-02-04 04:44:20 +0000 |
| commit | b5e945c260975c25c5ee423c081c98b78d959e0a (patch) | |
| tree | a86808458f408f47ae0fff346cc096ebc571ae71 /llvm/lib | |
| parent | 7a2944efe118e58d164c16c9d8f4d4d626a9f11d (diff) | |
| download | bcm5719-llvm-b5e945c260975c25c5ee423c081c98b78d959e0a.tar.gz bcm5719-llvm-b5e945c260975c25c5ee423c081c98b78d959e0a.zip | |
Recommit r352660 "[X86] Mark EMMS and FEMMS as clobbering MM0-7 and ST0-7."
We now print ST0 as 'st' when generating the clobber list for MS inline assembly in clang. This matches what the gcc reg name list expects.
Original commit message:
This fixes the test case in PR35982 by preventing MMX instructions that read MM0-7 from being moved below EMMS/FEMMS by the post RA scheduler.
Though as discussed in bugzilla, this is not a complete fix. There is still the possibility of reordering in IR or by the pre-RA scheduler.
Differential Revision: https://reviews.llvm.org/D57298
llvm-svn: 353016
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86Instr3DNow.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrMMX.td | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86Instr3DNow.td b/llvm/lib/Target/X86/X86Instr3DNow.td index af4a22adc21..cd1b0636597 100644 --- a/llvm/lib/Target/X86/X86Instr3DNow.td +++ b/llvm/lib/Target/X86/X86Instr3DNow.td @@ -73,7 +73,9 @@ defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr", WriteFAdd, 1>; defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd", WriteCvtI2PS>; defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", SchedWriteVecIMul.MMX, 1>; -let SchedRW = [WriteEMMS] in +let SchedRW = [WriteEMMS], + Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, + ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>, TB; diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td index 8e2a45b1bed..57835b1a256 100644 --- a/llvm/lib/Target/X86/X86InstrMMX.td +++ b/llvm/lib/Target/X86/X86InstrMMX.td @@ -152,7 +152,9 @@ multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC, // MMX EMMS Instruction //===----------------------------------------------------------------------===// -let SchedRW = [WriteEMMS] in +let SchedRW = [WriteEMMS], + Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, + ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>; //===----------------------------------------------------------------------===// |
