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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-10-24 00:27:00 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-10-24 00:27:00 +0000 |
| commit | b4a1347be2f2493217a1e9596deae7a5a3248563 (patch) | |
| tree | 6fa8e214a768c93371f728419d3e61f19c7fdbdb /llvm/lib | |
| parent | e2871d69dbfdb8e12f677f59ec690b54a18d8188 (diff) | |
| download | bcm5719-llvm-b4a1347be2f2493217a1e9596deae7a5a3248563.tar.gz bcm5719-llvm-b4a1347be2f2493217a1e9596deae7a5a3248563.zip | |
Add some asserts to catch copyRegToReg() fails early
llvm-svn: 84983
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/LowerSubregs.cpp | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/LowerSubregs.cpp b/llvm/lib/CodeGen/LowerSubregs.cpp index 8486bb084fe..8a0785d84a0 100644 --- a/llvm/lib/CodeGen/LowerSubregs.cpp +++ b/llvm/lib/CodeGen/LowerSubregs.cpp @@ -195,7 +195,9 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { // Insert sub-register copy const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); + bool Emitted = TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); + (void)Emitted; + assert(Emitted && "Subreg and Dst must be of compatible register class"); // Transfer the kill/dead flags, if needed. if (MI->getOperand(0).isDead()) TransferDeadFlag(MI, DstSubReg, TRI); @@ -209,7 +211,7 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { DEBUG(errs() << '\n'); MBB->erase(MI); - return true; + return true; } bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { @@ -264,8 +266,11 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { // KILL. BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(TargetInstrInfo::KILL), DstSubReg); - else - TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); + else { + bool Emitted = TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); + (void)Emitted; + assert(Emitted && "Subreg and Dst must be of compatible register class"); + } MachineBasicBlock::iterator CopyMI = MI; --CopyMI; |
