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| author | Nirav Dave <niravd@google.com> | 2019-01-24 17:47:18 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2019-01-24 17:47:18 +0000 |
| commit | b41a1984728725e955d7a4d9e8a8cfda7f40640c (patch) | |
| tree | d6a26ad6f5f63328d0c849308b6a3cefd69009d9 /llvm/lib | |
| parent | 47c0eb2bc2f604e765781263a0ec32811b186534 (diff) | |
| download | bcm5719-llvm-b41a1984728725e955d7a4d9e8a8cfda7f40640c.tar.gz bcm5719-llvm-b41a1984728725e955d7a4d9e8a8cfda7f40640c.zip | |
[InlineAsm] Don't calculate registers for inline asm memory operands. NFCI.
llvm-svn: 352066
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index f22ca4b55c3..664cc3b9900 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -7345,6 +7345,10 @@ static void GetRegistersForValue(SelectionDAG &DAG, const SDLoc &DL, SmallVector<unsigned, 4> Regs; const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); + // No work to do for memory operations. + if (OpInfo.ConstraintType == TargetLowering::C_Memory) + return; + // If this is a constraint for a single physreg, or a constraint for a // register class, find it. unsigned AssignedReg; |
