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| author | Nicolai Haehnle <nhaehnle@gmail.com> | 2018-06-21 13:36:08 +0000 |
|---|---|---|
| committer | Nicolai Haehnle <nhaehnle@gmail.com> | 2018-06-21 13:36:08 +0000 |
| commit | b3a9b685132a19d3b5252cca6d0b5569c848451c (patch) | |
| tree | 9529b737efcdc6d87fa81f79f0b173aa62554fcf /llvm/lib | |
| parent | f2674319018151e00f603ebab34ab2155f669394 (diff) | |
| download | bcm5719-llvm-b3a9b685132a19d3b5252cca6d0b5569c848451c.tar.gz bcm5719-llvm-b3a9b685132a19d3b5252cca6d0b5569c848451c.zip | |
AMDGPU: Add implicit def of SCC to kill and indirect pseudos
Summary:
Kill instructions sometimes do use SCC in unusual circumstances, when
v_cmpx cannot be used due to the operands that are involved.
Additionally, even if SCC was never defined by the expansion, kill pseudos
could previously occur between an s_cmp and an s_cbranch_scc, which breaks
the SCC liveness tracking when the pseudo is expanded to split the basic
block. While it would be possible to explicitly mark the SCC as live-in for
the successor basic block, it's simpler to just mark the pseudo as using SCC,
so that such a sequence is never emitted by instruction selection in the
first place.
A similar issue affects indirect source/dest pseudos in principle, although
I haven't been able to come up with a test case where it actually matters
(this affects instruction selection, so a MIR test can't be used).
Fixes: dEQP-GLES3.functional.shaders.discard.dynamic_loop_always
Change-Id: Ica8d82ecff1a763b892a1112cf1b06c948863a4f
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D47761
llvm-svn: 335223
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index a3b4ea008fe..87a891bb361 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -292,14 +292,21 @@ def SI_ELSE_BREAK : CFPseudoInstSI < let isReMaterializable = 1; } -let Uses = [EXEC], Defs = [EXEC,VCC] in { +let Uses = [EXEC] in { multiclass PseudoInstKill <dag ins> { + // Even though this pseudo can usually be expanded without an SCC def, we + // conservatively assume that it has an SCC def, both because it is sometimes + // required in degenerate cases (when V_CMPX cannot be used due to constant + // bus limitations) and because it allows us to avoid having to track SCC + // liveness across basic blocks. + let Defs = [EXEC,VCC,SCC] in def _PSEUDO : PseudoInstSI <(outs), ins> { let isConvergent = 1; let usesCustomInserter = 1; } + let Defs = [EXEC,VCC,SCC] in def _TERMINATOR : SPseudoInstSI <(outs), ins> { let isTerminator = 1; } @@ -308,6 +315,7 @@ multiclass PseudoInstKill <dag ins> { defm SI_KILL_I1 : PseudoInstKill <(ins SSrc_b64:$src, i1imm:$killvalue)>; defm SI_KILL_F32_COND_IMM : PseudoInstKill <(ins VSrc_b32:$src0, i32imm:$src1, i32imm:$cond)>; +let Defs = [EXEC,VCC] in def SI_ILLEGAL_COPY : SPseudoInstSI < (outs unknown:$dst), (ins unknown:$src), [], " ; illegal copy $src to $dst">; @@ -445,7 +453,7 @@ def ADJCALLSTACKDOWN : SPseudoInstSI< let usesCustomInserter = 1; } -let Defs = [M0, EXEC], +let Defs = [M0, EXEC, SCC], UseNamedOperandTable = 1 in { class SI_INDIRECT_SRC<RegisterClass rc> : VPseudoInstSI < |

