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| author | Michael Kuperstein <michael.m.kuperstein@intel.com> | 2015-11-04 11:17:53 +0000 |
|---|---|---|
| committer | Michael Kuperstein <michael.m.kuperstein@intel.com> | 2015-11-04 11:17:53 +0000 |
| commit | b34de72269ee8bd92917465328c17aa7ece9f581 (patch) | |
| tree | 8ee149e1402766b8c74b7a6ca84849d24069cb97 /llvm/lib | |
| parent | 3d7d92283274d835463d35829c3e6523f153612a (diff) | |
| download | bcm5719-llvm-b34de72269ee8bd92917465328c17aa7ece9f581.tar.gz bcm5719-llvm-b34de72269ee8bd92917465328c17aa7ece9f581.zip | |
[X86] DAGCombine should not introduce FILD in soft-float mode
The x86 "sitofp i64 to double" dag combine, in 32-bit mode, lowers sitofp
directly to X86ISD::FILD (or FILD_FLAG). This should not be done in soft-float mode.
llvm-svn: 252042
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4240aaafe57..3434f8c7f0b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -26419,8 +26419,8 @@ static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, } // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have - // a 32-bit target where SSE doesn't support i64->FP operations. - if (Op0.getOpcode() == ISD::LOAD) { + // a 32-bit target where SSE doesn't support i64->FP operations. + if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) { LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); EVT LdVT = Ld->getValueType(0); |
