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authorColin LeMahieu <colinl@codeaurora.org>2014-12-09 20:36:53 +0000
committerColin LeMahieu <colinl@codeaurora.org>2014-12-09 20:36:53 +0000
commitb030c254c05cfc7f8f0d681fd541cee9ad21f8f5 (patch)
tree86e3e4d2cb99e138c958ab4c588b0d6abef0c14b /llvm/lib
parent5dec7eaae2b3021b0858b5346c96f6b0001e3712 (diff)
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[Hexagon] Fixing broken tests.
llvm-svn: 223823
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.td3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
index 1399480c1d7..ab05ec51b3f 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -610,7 +610,8 @@ def C2_cmovenewif : T_TFRI_Pred<1, 1>;
let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
- isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
+ isPredicated = 0, isPredicable = 1, isReMaterializable = 1,
+ isCodeGenOnly = 0 in
def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
[(set (i32 IntRegs:$Rd), s16ExtPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
ImmRegRel, PredRel {
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