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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-10-11 17:54:15 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-10-11 17:54:15 +0000 |
| commit | af6c15f67916c30acda3aed908382230882ee03c (patch) | |
| tree | deb6b4791401654f20f3a7199d24eec8795ba259 /llvm/lib | |
| parent | 6aacd968754341a0743a427d842cacb91637279c (diff) | |
| download | bcm5719-llvm-af6c15f67916c30acda3aed908382230882ee03c.tar.gz bcm5719-llvm-af6c15f67916c30acda3aed908382230882ee03c.zip | |
[X86][SSE] Add support for v4i8 add reduction
llvm-svn: 374579
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index ad0f7134c25..38b6b96f3d7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -36239,10 +36239,15 @@ static SDValue combineReductionToHorizontal(SDNode *ExtElt, SelectionDAG &DAG, SDLoc DL(ExtElt); - if (VecVT == MVT::v8i8) { + // vXi8 reduction - sub 128-bit vector. + if (VecVT == MVT::v4i8 || VecVT == MVT::v8i8) { + // Pad with zero. + if (VecVT == MVT::v4i8) + Rdx = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i8, Rdx, + DAG.getConstant(0, DL, VecVT)); // Pad with undef. Rdx = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, Rdx, - DAG.getUNDEF(VecVT)); + DAG.getUNDEF(MVT::v8i8)); Rdx = DAG.getNode(X86ISD::PSADBW, DL, MVT::v2i64, Rdx, DAG.getConstant(0, DL, MVT::v16i8)); Rdx = DAG.getBitcast(MVT::v16i8, Rdx); |
