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| author | Zi Xuan Wu <wuzish@cn.ibm.com> | 2019-04-12 05:21:31 +0000 |
|---|---|---|
| committer | Zi Xuan Wu <wuzish@cn.ibm.com> | 2019-04-12 05:21:31 +0000 |
| commit | ac79ef8f0ec23aaaf485ec2da4ef7cadd36e3aa6 (patch) | |
| tree | d9af13064f5c4a678e4acd4b85bca94118202ef6 /llvm/lib | |
| parent | aa1cad1591bf4fd55b0d7f28e616329c4943e27d (diff) | |
| download | bcm5719-llvm-ac79ef8f0ec23aaaf485ec2da4ef7cadd36e3aa6.tar.gz bcm5719-llvm-ac79ef8f0ec23aaaf485ec2da4ef7cadd36e3aa6.zip | |
[PowerPC] More precise exploitation of P9 maddld instruction when operands are constant
There are 3 operands of maddld, (add (mul %1, %2), %3) and sometimes
they are constant. If there is constant operand, it takes extra li to
materialize the operand, and one more extra register too. So it's not
profitable to use maddld to optimize mul-add pattern.
Differential Revision: https://reviews.llvm.org/D60181
llvm-svn: 358253
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.td | 11 |
2 files changed, 13 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 42e4ce7172a..256e62f7d21 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -777,7 +777,7 @@ def MADDHDU : VAForm_1a<49, "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, - [(set i32:$RT, (add (mul i32:$RA, i32:$RB), i32:$RC))]>, + [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, isPPC64; def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; @@ -785,7 +785,7 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in { def MADDLD8 : VAForm_1a<51, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, - [(set i64:$RT, (add (mul i64:$RA, i64:$RB), i64:$RC))]>, + [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, isPPC64; def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA), "setb $RT, $BFA", IIC_IntGeneral>, isPPC64; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index e9bc47efc5a..5b541f2bb03 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -457,6 +457,17 @@ def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), return !isOffsetMultipleOf(N, 16); }]>; +// PatFrag for binary operation whose operands are both non-constant +class BinOpWithoutSImm16Operand<SDNode opcode> : + PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ + int16_t Imm; + return !isIntS16Immediate(N->getOperand(0), Imm) + && !isIntS16Immediate(N->getOperand(1), Imm); +}]>; + +def add_without_simm16 : BinOpWithoutSImm16Operand<add>; +def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; + //===----------------------------------------------------------------------===// // PowerPC Flag Definitions. |
