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| author | Tom Stellard <tstellar@redhat.com> | 2018-07-13 22:16:03 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2018-07-13 22:16:03 +0000 |
| commit | ac68471326c9abd93b97e6158f00e46607c3b260 (patch) | |
| tree | 80b4184301acb334efe187a22a01c486030a0d14 /llvm/lib | |
| parent | da424ba1c5ead401270aa64891cbf9a2791b08c4 (diff) | |
| download | bcm5719-llvm-ac68471326c9abd93b97e6158f00e46607c3b260.tar.gz bcm5719-llvm-ac68471326c9abd93b97e6158f00e46607c3b260.zip | |
AMDGPU/GlobalISel: Implement select() for 32-bit @llvm.minnun and @llvm.maxnum
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D46172
llvm-svn: 337056
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 17 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 2 |
2 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td index fd1b29384ce..ba735390f67 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -85,6 +85,18 @@ class GISelVop3Pat2CommutePat < (inst src0_vt:$src1, src1_vt:$src0) >; +class GISelVop3Pat2ModsPat < + SDPatternOperator node, + Instruction inst, + ValueType dst_vt, + ValueType src0_vt = dst_vt, ValueType src1_vt = src0_vt> : GCNPat < + + (dst_vt (node (src0_vt (VOP3Mods0 src0_vt:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omods)), + (src1_vt (VOP3Mods src1_vt:$src1, i32:$src1_modifiers)))), + (inst i32:$src0_modifiers, src0_vt:$src0, + i32:$src1_modifiers, src1_vt:$src1, $clamp, $omods) +>; + multiclass GISelVop2IntrPat < SDPatternOperator node, Instruction inst, ValueType dst_vt, ValueType src_vt = dst_vt> { @@ -119,3 +131,8 @@ def : GISelVop3Pat2CommutePat <sra, V_ASHRREV_I32_e64, i32>; // this is even supported yet. defm : GISelVop2IntrPat < int_amdgcn_cvt_pkrtz, V_CVT_PKRTZ_F16_F32_e32, v2f16, f32>; + +defm : GISelVop2IntrPat <int_maxnum, V_MAX_F32_e32, f32>; +def : GISelVop3Pat2ModsPat <int_maxnum, V_MAX_F64, f64>; +defm : GISelVop2IntrPat <int_minnum, V_MIN_F32_e32, f32>; +def : GISelVop3Pat2ModsPat <int_minnum, V_MIN_F64, f64>; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 7db6edc5575..219d430fbb3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -186,6 +186,8 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I, switch (IntrinsicID) { default: break; + case Intrinsic::maxnum: + case Intrinsic::minnum: case Intrinsic::amdgcn_cvt_pkrtz: return selectImpl(I, CoverageInfo); |
