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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-12-02 19:45:05 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-12-02 19:45:05 +0000 |
| commit | ab256185da704b39b55a019ed1f7e1e2585e83d9 (patch) | |
| tree | f7daca6437956dd643fd7f02233bbbec78d0ec0d /llvm/lib | |
| parent | f61232264edf56ce6f3ae3208f8dbca670e7b329 (diff) | |
| download | bcm5719-llvm-ab256185da704b39b55a019ed1f7e1e2585e83d9.tar.gz bcm5719-llvm-ab256185da704b39b55a019ed1f7e1e2585e83d9.zip | |
R600/SI: Refactor AMDGPUAsmPrinter::EmitProgramInfoSI()
llvm-svn: 223144
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp index 5511d7c6f8f..b2ee3c8aa50 100644 --- a/llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp @@ -358,19 +358,21 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo, ProgInfo.CodeLen = CodeSize; } +static unsigned getRsrcReg(unsigned ShaderType) { + switch (ShaderType) { + default: // Fall through + case ShaderType::COMPUTE: return R_00B848_COMPUTE_PGM_RSRC1; + case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS; + case ShaderType::PIXEL: return R_00B028_SPI_SHADER_PGM_RSRC1_PS; + case ShaderType::VERTEX: return R_00B128_SPI_SHADER_PGM_RSRC1_VS; + } +} + void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF, const SIProgramInfo &KernelInfo) { const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>(); const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>(); - - unsigned RsrcReg; - switch (MFI->getShaderType()) { - default: // Fall through - case ShaderType::COMPUTE: RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break; - case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break; - case ShaderType::PIXEL: RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break; - case ShaderType::VERTEX: RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break; - } + unsigned RsrcReg = getRsrcReg(MFI->getShaderType()); unsigned LDSAlignShift; if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) { |
