implement uncond branch insertion, mark branches with isBranch.

llvm-svn: 31160

3 files changed, 13 insertions, 1 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index 810c254f9c0..c61d83630c9 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -48,3 +48,11 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
   }
   return false;
 }
+
+void ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
+                                  MachineBasicBlock *FBB,
+                                  const std::vector<MachineOperand> &Cond)const{
+  // Can only insert uncond branches so far.
+  assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
+  BuildMI(&MBB, ARM::b, 1).addMBB(TBB);
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.h b/llvm/lib/Target/ARM/ARMInstrInfo.h
index 6318caa8db0..0621c70d14b 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.h
@@ -40,6 +40,10 @@ public:
   ///
   virtual bool isMoveInstr(const MachineInstr &MI,
                            unsigned &SrcReg, unsigned &DstReg) const;
+
+  virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                            MachineBasicBlock *FBB,
+                            const std::vector<MachineOperand> &Cond) const;
 };
 
 }
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index 816970f1169..f2100e11ca4 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -227,7 +227,7 @@ let Defs = [R0] in {
   def UMULL   : IntBinOp<"umull r12,", mulhu>;
 }
 
-let isTerminator = 1 in {
+let isTerminator = 1, isBranch = 1 in {
   def bcond   : InstARM<(ops brtarget:$dst, CCOp:$cc),
 	                    "b$cc $dst",
 		            [(armbr bb:$dst, imm:$cc)]>;