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author | Quentin Colombet <qcolombet@apple.com> | 2016-04-07 21:32:23 +0000 |
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committer | Quentin Colombet <qcolombet@apple.com> | 2016-04-07 21:32:23 +0000 |
commit | aac71a4a0eb420173239a6acb6d192570c974464 (patch) | |
tree | 17e4fff1683d0b21c3e72c9e39dab9b9a94e50a3 /llvm/lib | |
parent | c53ad4f3b2b001e476010690e6cc42e8a3ea458e (diff) | |
download | bcm5719-llvm-aac71a4a0eb420173239a6acb6d192570c974464.tar.gz bcm5719-llvm-aac71a4a0eb420173239a6acb6d192570c974464.zip |
[RegBankSelect] Reuse RegisterBankInfo logic to get to the register bank
from a register.
On top of duplicating the logic, it was buggy! It would assert on
physical registers, since MachineRegisterInfo does not have any
information regarding register classes/banks for them.
llvm-svn: 265727
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp index b4179233036..4e0650e04f9 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -33,6 +33,7 @@ void RegBankSelect::init(MachineFunction &MF) { RBI = MF.getSubtarget().getRegBankInfo(); assert(RBI && "Cannot work without RegisterBankInfo"); MRI = &MF.getRegInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); MIRBuilder.setMF(MF); } @@ -43,18 +44,7 @@ bool RegBankSelect::assignmentMatch( if (ValMapping.BreakDown.size() > 1) return false; - const RegClassOrRegBank &CurAssignment = MRI->getRegClassOrRegBank(Reg); - // Nothing assigned, the assignment does not match. - if (!CurAssignment) - return false; - // Get the register bank form the current assignment. - const RegisterBank *CurRegBank = nullptr; - if (CurAssignment.is<const TargetRegisterClass *>()) - CurRegBank = &RBI->getRegBankFromRegClass( - *CurAssignment.get<const TargetRegisterClass *>()); - else - CurRegBank = CurAssignment.get<const RegisterBank *>(); - return CurRegBank == ValMapping.BreakDown[0].RegBank; + return RBI->getRegBank(Reg, *MRI, *TRI) == ValMapping.BreakDown[0].RegBank; } unsigned |