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authorLang Hames <lhames@gmail.com>2012-04-02 19:58:43 +0000
committerLang Hames <lhames@gmail.com>2012-04-02 19:58:43 +0000
commitaaafacd07ed17080f399a2613702f48b8fad1bb8 (patch)
treecd94b8a54cac747de87b48de32dc9e4747750c5b /llvm/lib
parentd6fbc8ff664f39fb7b72ac4b21020e743cf410a1 (diff)
downloadbcm5719-llvm-aaafacd07ed17080f399a2613702f48b8fad1bb8.tar.gz
bcm5719-llvm-aaafacd07ed17080f399a2613702f48b8fad1bb8.zip
During two-address lowering, rescheduling an instruction does not untie
operands. Make TryInstructionTransform return false to reflect this. Fixes PR11861. llvm-svn: 153892
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/TwoAddressInstructionPass.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 24b8bc2048a..789617ba7fc 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1248,7 +1248,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
// re-schedule this MI below it.
if (RescheduleMIBelowKill(mbbi, mi, nmi, regB)) {
++NumReSchedDowns;
- return true;
+ return false;
}
if (TargetRegisterInfo::isVirtualRegister(regA))
@@ -1270,7 +1270,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
// re-schedule it before this MI if it's legal.
if (RescheduleKillAboveMI(mbbi, mi, nmi, regB)) {
++NumReSchedUps;
- return true;
+ return false;
}
// If this is an instruction with a load folded into it, try unfolding
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