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author | Peter Collingbourne <peter@pcc.me.uk> | 2018-04-10 16:19:30 +0000 |
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committer | Peter Collingbourne <peter@pcc.me.uk> | 2018-04-10 16:19:30 +0000 |
commit | a7d936f0c06498996eab6e6e137880291a5bb776 (patch) | |
tree | 3893f5ba1e4ea878ac031c2673dcc6ce7c32326f /llvm/lib | |
parent | 80ba43872e4b2432d9dba40919c8a14da3744af7 (diff) | |
download | bcm5719-llvm-a7d936f0c06498996eab6e6e137880291a5bb776.tar.gz bcm5719-llvm-a7d936f0c06498996eab6e6e137880291a5bb776.zip |
Revert r329611, "AArch64: Allow offsets to be folded into addresses with ELF."
Caused a build failure in check-tsan.
llvm-svn: 329718
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 18 | ||||
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 23 |
2 files changed, 17 insertions, 24 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index d44eee051aa..eee59f1e719 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -743,16 +743,14 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size, if (!GAN) return true; - if (GAN->getOffset() % Size == 0) { - const GlobalValue *GV = GAN->getGlobal(); - unsigned Alignment = GV->getAlignment(); - Type *Ty = GV->getValueType(); - if (Alignment == 0 && Ty->isSized()) - Alignment = DL.getABITypeAlignment(Ty); - - if (Alignment >= Size) - return true; - } + const GlobalValue *GV = GAN->getGlobal(); + unsigned Alignment = GV->getAlignment(); + Type *Ty = GV->getValueType(); + if (Alignment == 0 && Ty->isSized()) + Alignment = DL.getABITypeAlignment(Ty); + + if (Alignment >= Size) + return true; } if (CurDAG->isBaseWithConstantOffset(N)) { diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 546da27cc41..28edcc2e47b 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -3675,8 +3675,7 @@ AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, SDValue AArch64TargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const { - return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, - N->getOffset(), Flag); + return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); } SDValue AArch64TargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, @@ -3750,9 +3749,9 @@ SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op, : AArch64II::MO_NO_FLAG); unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); - if (OpFlags != AArch64II::MO_NO_FLAG) - assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 && - "unexpected offset in global node"); + + assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 && + "unexpected offset in global node"); // This also catches the large code model case for Darwin. if ((OpFlags & AArch64II::MO_GOT) != 0) { @@ -4990,15 +4989,11 @@ SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op, bool AArch64TargetLowering::isOffsetFoldingLegal( const GlobalAddressSDNode *GA) const { - // FIXME: Only ELF can represent the full range of possible addends here, as - // the format stores the addend in a 64-bit field. With Mach-O the equivalent - // field is 24 bits, and with COFF it is 21 bits. To make this work with the - // other object formats we will need to arrange to prevent the addend from - // going out of bounds. - if (!getTargetMachine().getTargetTriple().isOSBinFormatELF()) - return false; - return Subtarget->ClassifyGlobalReference( - GA->getGlobal(), getTargetMachine()) == AArch64II::MO_NO_FLAG; + DEBUG(dbgs() << "Skipping offset folding global address: "); + DEBUG(GA->dump()); + DEBUG(dbgs() << "AArch64 doesn't support folding offsets into global " + "addresses\n"); + return false; } bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { |