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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-15 17:26:43 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-07-15 17:26:43 +0000 |
| commit | a65913e752e00f97df20aec6bbd3fea78fef973c (patch) | |
| tree | 15bf8b6718a3396d67fddc2ff6e5d6e1bfae4631 /llvm/lib | |
| parent | cc02b170823575049a13f22ccf3529a289625f89 (diff) | |
| download | bcm5719-llvm-a65913e752e00f97df20aec6bbd3fea78fef973c.tar.gz bcm5719-llvm-a65913e752e00f97df20aec6bbd3fea78fef973c.zip | |
AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTOR
llvm-svn: 366087
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 5b2dfc8ff50..6b827db6faa 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -341,6 +341,9 @@ bool AMDGPUInstructionSelector::selectG_MERGE_VALUES(MachineInstr &MI) const { LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); const unsigned SrcSize = SrcTy.getSizeInBits(); + if (SrcSize < 32) + return false; + const DebugLoc &DL = MI.getDebugLoc(); const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, TRI); const unsigned DstSize = DstTy.getSizeInBits(); @@ -1235,6 +1238,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I, case TargetOpcode::G_EXTRACT: return selectG_EXTRACT(I); case TargetOpcode::G_MERGE_VALUES: + case TargetOpcode::G_BUILD_VECTOR: case TargetOpcode::G_CONCAT_VECTORS: return selectG_MERGE_VALUES(I); case TargetOpcode::G_UNMERGE_VALUES: |
