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| author | Craig Topper <craig.topper@intel.com> | 2018-05-29 06:22:45 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-05-29 06:22:45 +0000 |
| commit | a34f8731c7c3f96e3532b8e51ae275ce6fd78f3c (patch) | |
| tree | b7f733413984fc277e9e41a7b3370b9e9526297c /llvm/lib | |
| parent | 07c9ec6f2e8d06ac0fd2a01df2c50c533e8458c3 (diff) | |
| download | bcm5719-llvm-a34f8731c7c3f96e3532b8e51ae275ce6fd78f3c.tar.gz bcm5719-llvm-a34f8731c7c3f96e3532b8e51ae275ce6fd78f3c.zip | |
[X86] Disable a DAG combine to allow packed AVX512DQ instructions to be consistently used for i64->float/double conversions.
Summary: We already get this right if the i64 didn't come from a load.
Reviewers: RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47439
llvm-svn: 333393
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 15eeddf0faa..38649b8fdf0 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -37729,6 +37729,11 @@ static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG, if (VT == MVT::f16 || VT == MVT::f128) return SDValue(); + // If we have AVX512DQ we can use packed conversion instructions unless + // the VT is f80. + if (Subtarget.hasDQI() && VT != MVT::f80) + return SDValue(); + if (!Ld->isVolatile() && !VT.isVector() && ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && !Subtarget.is64Bit() && LdVT == MVT::i64) { |
