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| author | Igor Breger <igor.breger@intel.com> | 2016-09-05 08:26:51 +0000 |
|---|---|---|
| committer | Igor Breger <igor.breger@intel.com> | 2016-09-05 08:26:51 +0000 |
| commit | a2f8ca9a34f5635df0a842010dc69ef95a723b7d (patch) | |
| tree | 0af3a2159e318f73130bed10aa92cf766a53d5ee /llvm/lib | |
| parent | 428169a5d61066bcc33bc1f11d2d073a284d0fba (diff) | |
| download | bcm5719-llvm-a2f8ca9a34f5635df0a842010dc69ef95a723b7d.tar.gz bcm5719-llvm-a2f8ca9a34f5635df0a842010dc69ef95a723b7d.zip | |
[AVX512] Fix v8i1 /v16i1 zext + bitcast lowering pattern. Explicitly zero upper bits.
Differential Revision: http://reviews.llvm.org/D23983
llvm-svn: 280650
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 78cd5878662..59218bcf552 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -2117,15 +2117,15 @@ def : Pat<(i8 (bitconvert (v8i1 VK8:$src))), (COPY_TO_REGCLASS VK8:$src, GR8)>; def : Pat<(i32 (zext (i16 (bitconvert (v16i1 VK16:$src))))), - (i32 (SUBREG_TO_REG (i64 0), - (i16 (COPY_TO_REGCLASS VK16:$src, GR16)), sub_16bit))>; + (KMOVWrk VK16:$src)>; def : Pat<(i32 (anyext (i16 (bitconvert (v16i1 VK16:$src))))), (i32 (SUBREG_TO_REG (i64 0), (i16 (COPY_TO_REGCLASS VK16:$src, GR16)), sub_16bit))>; def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))), - (i32 (SUBREG_TO_REG (i64 0), - (i8 (COPY_TO_REGCLASS VK8:$src, GR8)), sub_8bit))>; + (MOVZX32rr8 (COPY_TO_REGCLASS VK8:$src, GR8))>, Requires<[NoDQI]>; +def : Pat<(i32 (zext (i8 (bitconvert (v8i1 VK8:$src))))), + (KMOVBrk VK8:$src)>, Requires<[HasDQI]>; def : Pat<(i32 (anyext (i8 (bitconvert (v8i1 VK8:$src))))), (i32 (SUBREG_TO_REG (i64 0), (i8 (COPY_TO_REGCLASS VK8:$src, GR8)), sub_8bit))>; |
