[X86] Remove the vector alignment requirement from the patterns added in r337320.

The resulting instruction will only load 64 bits so alignment isn't required.

llvm-svn: 337334

1 files changed, 4 insertions, 2 deletions

diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 3797d91fb31..c8ad7d9eabb 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -725,7 +725,8 @@ let Predicates = [UseSSE1] in {
 
   // This pattern helps select MOVLPS on SSE1 only targets. With SSE2 we'll
   // end up with a movsd or bleand instead of shufp.
-  def : Pat<(X86Shufp (memopv4f32 addr:$src2), VR128:$src1, (i8 -28)),
+  // No need for aligned load, we're only loading 64-bits.
+  def : Pat<(X86Shufp (loadv4f32 addr:$src2), VR128:$src1, (i8 -28)),
             (MOVLPSrm VR128:$src1, addr:$src2)>;
 }
 
@@ -801,7 +802,8 @@ let Predicates = [UseSSE1] in {
 
   // This pattern helps select MOVHPS on SSE1 only targets. With SSE2 we'll
   // end up with a movsd or bleand instead of shufp.
-  def : Pat<(X86Movlhps VR128:$src1, (memopv4f32 addr:$src2)),
+  // No need for aligned load, we're only loading 64-bits.
+  def : Pat<(X86Movlhps VR128:$src1, (loadv4f32 addr:$src2)),
             (MOVHPSrm VR128:$src1, addr:$src2)>;
 }