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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-26 17:55:09 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-26 17:55:09 +0000 |
| commit | a276c3e053768754162427465a7f01b357d8b7fc (patch) | |
| tree | 19438b16719f7459474ed22926dc50960f65f189 /llvm/lib | |
| parent | ee522bf23eb1416b99e0234fe6fe1fe5f4086f35 (diff) | |
| download | bcm5719-llvm-a276c3e053768754162427465a7f01b357d8b7fc.tar.gz bcm5719-llvm-a276c3e053768754162427465a7f01b357d8b7fc.zip | |
R600/SI: Add a note about the order of the operands to div_scale
llvm-svn: 218534
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUISelLowering.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp index 29d3fc38e57..32bab66aeed 100644 --- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp @@ -825,6 +825,12 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, // first parameter must be the same as the first instruction. SDValue Numerator = Op.getOperand(1); SDValue Denominator = Op.getOperand(2); + + // Note this order is opposite of the machine instruction's operations, + // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The + // intrinsic has the numerator as the first operand to match a normal + // division operation. + SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator; return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0, |
