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| author | Craig Topper <craig.topper@intel.com> | 2018-11-30 08:32:05 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-11-30 08:32:05 +0000 |
| commit | a2133061c01506cace7a365f29e373bae8769639 (patch) | |
| tree | 75591eea9713c0a6dd14a21bbc370851b85856af /llvm/lib | |
| parent | 6e4b266a0d0aae8084908be011d1d696fc35c89d (diff) | |
| download | bcm5719-llvm-a2133061c01506cace7a365f29e373bae8769639.tar.gz bcm5719-llvm-a2133061c01506cace7a365f29e373bae8769639.zip | |
[X86] Emit PACKUS directly from the v16i8 LowerMULH code instead of using a shuffle.
llvm-svn: 347967
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 7298c208cbb..0035335a2a7 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -23766,12 +23766,7 @@ static SDValue LowerMULH(SDValue Op, const X86Subtarget &Subtarget, RHi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ExVT, RHi, 8, DAG); // Bitcast back to VT and then pack all the even elements from Lo and Hi. - // Shuffle lowering should turn this into PACKUS. - RLo = DAG.getBitcast(VT, RLo); - RHi = DAG.getBitcast(VT, RHi); - return DAG.getVectorShuffle(VT, dl, RLo, RHi, - { 0, 2, 4, 6, 8, 10, 12, 14, - 16, 18, 20, 22, 24, 26, 28, 30}); + return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi); } SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const { |
