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| author | Amara Emerson <aemerson@apple.com> | 2019-03-18 21:29:21 +0000 |
|---|---|---|
| committer | Amara Emerson <aemerson@apple.com> | 2019-03-18 21:29:21 +0000 |
| commit | a140276a1e0fa035115d64749251d92aad273c1f (patch) | |
| tree | 9c7230c61ed33facd05303a608519e329cbfb2eb /llvm/lib | |
| parent | b7708ec87fcfaaa1526469bd010cb10f9b9f1495 (diff) | |
| download | bcm5719-llvm-a140276a1e0fa035115d64749251d92aad273c1f.tar.gz bcm5719-llvm-a140276a1e0fa035115d64749251d92aad273c1f.zip | |
[GlobalISel] Include missing change from r356396
Forgot to add a change to relax some asserts in r356396.
llvm-svn: 356411
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 81d26e6addb..bc3d805dbd6 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -912,10 +912,8 @@ MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc, } case TargetOpcode::COPY: assert(DstOps.size() == 1 && "Invalid Dst"); - assert(SrcOps.size() == 1 && "Invalid Srcs"); - assert(DstOps[0].getLLTTy(*getMRI()) == LLT() || - SrcOps[0].getLLTTy(*getMRI()) == LLT() || - DstOps[0].getLLTTy(*getMRI()) == SrcOps[0].getLLTTy(*getMRI())); + // If the caller wants to add a subreg source it has to be done separately + // so we may not have any SrcOps at this point yet. break; case TargetOpcode::G_FCMP: case TargetOpcode::G_ICMP: { |
