diff options
| author | Craig Topper <craig.topper@intel.com> | 2018-01-07 23:56:37 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-07 23:56:37 +0000 |
| commit | 9f5859e3ee2a1788b7f9fd4924666755cb45d66e (patch) | |
| tree | fb3787fb5c9d43488cc2ae1327fc469fc7855ae3 /llvm/lib | |
| parent | 03d8e516cf55e0205ad5e32a8d05163c977196b1 (diff) | |
| download | bcm5719-llvm-9f5859e3ee2a1788b7f9fd4924666755cb45d66e.tar.gz bcm5719-llvm-9f5859e3ee2a1788b7f9fd4924666755cb45d66e.zip | |
[X86] Simplify some code in lower1BitVectorShuffle by relying on getNode's ability to constant fold vector SIGN_EXTEND.
llvm-svn: 321979
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 17 |
1 files changed, 2 insertions, 15 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index ca24d6df891..3c19960860d 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -14286,21 +14286,8 @@ static SDValue lower1BitVectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, break; } - if (ISD::isBuildVectorAllZeros(V1.getNode())) - V1 = getZeroVector(ExtVT, Subtarget, DAG, DL); - else if (ISD::isBuildVectorAllOnes(V1.getNode())) - V1 = getOnesVector(ExtVT, DAG, DL); - else - V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1); - - if (V2.isUndef()) - V2 = DAG.getUNDEF(ExtVT); - else if (ISD::isBuildVectorAllZeros(V2.getNode())) - V2 = getZeroVector(ExtVT, Subtarget, DAG, DL); - else if (ISD::isBuildVectorAllOnes(V2.getNode())) - V2 = getOnesVector(ExtVT, DAG, DL); - else - V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2); + V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1); + V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2); SDValue Shuffle = DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask); // i1 was sign extended we can use X86ISD::CVT2MASK. |
