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| author | Craig Topper <craig.topper@intel.com> | 2018-07-08 18:04:00 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-07-08 18:04:00 +0000 |
| commit | 9e17073c218602cbd9e4345ab7c3674ff500b06d (patch) | |
| tree | a9b48402ec46df9d38757f498210e74a0c767940 /llvm/lib | |
| parent | 2eced71ecf8d1bf69e219973f1bd5ac19375bb32 (diff) | |
| download | bcm5719-llvm-9e17073c218602cbd9e4345ab7c3674ff500b06d.tar.gz bcm5719-llvm-9e17073c218602cbd9e4345ab7c3674ff500b06d.zip | |
[X86] Enhance combineFMA to look for FNEG behind an EXTRACT_VECTOR_ELT.
llvm-svn: 336514
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 6d5923010cc..5c7b43cc086 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -37762,11 +37762,23 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG, SDValue B = N->getOperand(1); SDValue C = N->getOperand(2); - auto invertIfNegative = [](SDValue &V) { + auto invertIfNegative = [&DAG](SDValue &V) { if (SDValue NegVal = isFNEG(V.getNode())) { V = NegVal; return true; } + // Look through extract_vector_elts. If it comes from an FNEG, create a + // new extract from the FNEG input. + if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT && + isa<ConstantSDNode>(V.getOperand(1)) && + cast<ConstantSDNode>(V.getOperand(1))->getZExtValue() == 0) { + if (SDValue NegVal = isFNEG(V.getOperand(0).getNode())) { + V = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(V), V.getValueType(), + NegVal, V.getOperand(1)); + return true; + } + } + return false; }; |

