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| author | Eric Christopher <echristo@gmail.com> | 2014-07-23 22:12:03 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2014-07-23 22:12:03 +0000 |
| commit | 9d9167950e038bb2b7aa7f958f647b6e232583cc (patch) | |
| tree | 10ed99b64abc1e9297ee50514456ee4ea9b2d55f /llvm/lib | |
| parent | 8e9cfa549768d36b4b63aa4ac4686e1800281a90 (diff) | |
| download | bcm5719-llvm-9d9167950e038bb2b7aa7f958f647b6e232583cc.tar.gz bcm5719-llvm-9d9167950e038bb2b7aa7f958f647b6e232583cc.zip | |
Remove the query for TargetMachine and TargetInstrInfo since we're
already inside TargetInstrInfo.
llvm-svn: 213806
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/TargetInstrInfo.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index 83966bd0c20..fc74899f479 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -562,8 +562,6 @@ isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, AliasAnalysis *AA) const { const MachineFunction &MF = *MI->getParent()->getParent(); const MachineRegisterInfo &MRI = MF.getRegInfo(); - const TargetMachine &TM = MF.getTarget(); - const TargetInstrInfo &TII = *TM.getInstrInfo(); // Remat clients assume operand 0 is the defined register. if (!MI->getNumOperands() || !MI->getOperand(0).isReg()) @@ -582,7 +580,7 @@ isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, // redundant with subsequent checks, but it's target-independent, // simple, and a common case. int FrameIdx = 0; - if (TII.isLoadFromStackSlot(MI, FrameIdx) && + if (isLoadFromStackSlot(MI, FrameIdx) && MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx)) return true; |
