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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-30 15:58:56 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-30 15:58:56 +0000 |
| commit | 9cec221a1c087b3c02a4482a3c7cc6d6b450043d (patch) | |
| tree | fa9c2b818228a3421b6c388fc2a6aaac9d926d16 /llvm/lib | |
| parent | 99f436b0554a0ba1bf276eae93d83db3a7f674f2 (diff) | |
| download | bcm5719-llvm-9cec221a1c087b3c02a4482a3c7cc6d6b450043d.tar.gz bcm5719-llvm-9cec221a1c087b3c02a4482a3c7cc6d6b450043d.zip | |
[X86][BtVer2] Add the ability to add additional uops for folded instructions
Some instructions take an extra load uop - but not consistently.....
llvm-svn: 343410
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 88bb9605267..438f13eddd8 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -100,7 +100,8 @@ def : ReadAdvance<ReadAfterLd, 3>; // folded loads. multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW, list<ProcResourceKind> ExePorts, - int Lat, list<int> Res = [], int UOps = 1> { + int Lat, list<int> Res = [], int UOps = 1, + int LoadUOps = 0> { // Register variant is using a single cycle on ExePort. def : WriteRes<SchedRW, ExePorts> { let Latency = Lat; @@ -113,13 +114,14 @@ multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW, def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> { let Latency = !add(Lat, 3); let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); - let NumMicroOps = UOps; + let NumMicroOps = !add(UOps, LoadUOps); } } multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW, list<ProcResourceKind> ExePorts, - int Lat, list<int> Res = [], int UOps = 1> { + int Lat, list<int> Res = [], int UOps = 1, + int LoadUOps = 0> { // Register variant is using a single cycle on ExePort. def : WriteRes<SchedRW, ExePorts> { let Latency = Lat; @@ -132,13 +134,14 @@ multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW, def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> { let Latency = !add(Lat, 5); let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); - let NumMicroOps = UOps; + let NumMicroOps = !add(UOps, LoadUOps); } } multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW, list<ProcResourceKind> ExePorts, - int Lat, list<int> Res = [2], int UOps = 2> { + int Lat, list<int> Res = [2], int UOps = 2, + int LoadUOps = 0> { // Register variant is using a single cycle on ExePort. def : WriteRes<SchedRW, ExePorts> { let Latency = Lat; @@ -151,7 +154,7 @@ multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW, def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> { let Latency = !add(Lat, 5); let ResourceCycles = !listconcat([2], Res); - let NumMicroOps = UOps; + let NumMicroOps = !add(UOps, LoadUOps); } } |
