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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-08-11 23:08:22 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-08-11 23:08:22 +0000 |
| commit | 9c473e46f3846c8678d1d79911a8eb40e1c55bda (patch) | |
| tree | 0136c2a2d77b4ad45b46f56e4cb0791465aab119 /llvm/lib | |
| parent | cacb0e2d458187fbcf31ee95df9552df9d437955 (diff) | |
| download | bcm5719-llvm-9c473e46f3846c8678d1d79911a8eb40e1c55bda.tar.gz bcm5719-llvm-9c473e46f3846c8678d1d79911a8eb40e1c55bda.zip | |
Fix <rdar://problem/8282498> even if it doesn't reproduce on trunk.
When a register is defined by a partial load:
%reg1234:sub_32 = MOV32mr <fi#-1>; GR64:%reg1234
That load cannot be folded into an instruction using the full 64-bit register.
It would become a 64-bit load.
This is related to the recent change to have isLoadFromStackSlot return false on
a sub-register load.
llvm-svn: 110874
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 4ee0c0af835..7d973ea89d3 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -2410,6 +2410,11 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, } else if (Ops.size() != 1) return NULL; + // Make sure the subregisters match. + // Otherwise we risk changing the size of the load. + if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg()) + return NULL; + SmallVector<MachineOperand,X86::AddrNumOperands> MOs; switch (LoadMI->getOpcode()) { case X86::V_SET0PS: |
