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authorTim Northover <tnorthover@apple.com>2014-05-16 09:40:52 +0000
committerTim Northover <tnorthover@apple.com>2014-05-16 09:40:52 +0000
commit9c2b4c29ab4c7c8e8c19fd888a9805e2731724e7 (patch)
tree9c1b1b304fd8b140ca287c39ad3502dad799c820 /llvm/lib
parent8579f0d4d1dfb03439b24b1c3ec3ab44275ea406 (diff)
downloadbcm5719-llvm-9c2b4c29ab4c7c8e8c19fd888a9805e2731724e7.tar.gz
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ARM64: disable printing of "lslv" type aliases
You can write "lslv w0, w1, w2" (probably for legacy reasons), but it should be printed as simply "lsl". This will be tested when the TableGen "should I print this Alias" heuristic is fixed (very soon). llvm-svn: 208956
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM64/ARM64InstrFormats.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64InstrFormats.td b/llvm/lib/Target/ARM64/ARM64InstrFormats.td
index 875f0aebde3..8133a0084f7 100644
--- a/llvm/lib/Target/ARM64/ARM64InstrFormats.td
+++ b/llvm/lib/Target/ARM64/ARM64InstrFormats.td
@@ -1255,7 +1255,7 @@ multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
: InstAlias<asm#" $dst, $src1, $src2",
- (inst regtype:$dst, regtype:$src1, regtype:$src2)>;
+ (inst regtype:$dst, regtype:$src1, regtype:$src2), 0>;
class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
RegisterClass addtype, string asm,
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