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authorRoman Lebedev <lebedev.ri@gmail.com>2018-06-15 09:56:39 +0000
committerRoman Lebedev <lebedev.ri@gmail.com>2018-06-15 09:56:39 +0000
commit9c17dad8f2528ebb9505ab2e549cc25d307d0f2b (patch)
treec459ec7d41c6609a88179da60e424fa565c78d84 /llvm/lib
parentaa8587d1fcfba6b54a826d2590ddf477261b6800 (diff)
downloadbcm5719-llvm-9c17dad8f2528ebb9505ab2e549cc25d307d0f2b.tar.gz
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[AMDGPU] Recognize x & ((1 << y) - 1) pattern.
Summary: As a followup for D48007. Since we already handle `x << (bitwidth - y) >> (bitwidth - y)` pattern, which does not have ub for both the edge cases (`y == 0`, `y == bitwidth`), i think also handling a pattern that is ub for `y == bitwidth` should be fine. Reviewers: nhaehnle, bogner, tstellar, arsenm Reviewed By: arsenm Subscribers: arsenm, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #amdgpu Differential Revision: https://reviews.llvm.org/D48010 llvm-svn: 334816
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AMDGPU/AMDGPUInstructions.td7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 22a7a9c44a3..65d72fcb46f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -126,6 +126,7 @@ def or_oneuse : HasOneUseBinOp<or>;
def xor_oneuse : HasOneUseBinOp<xor>;
} // Properties = [SDNPCommutative, SDNPAssociative]
+def add_oneuse : HasOneUseBinOp<add>;
def sub_oneuse : HasOneUseBinOp<sub>;
def srl_oneuse : HasOneUseBinOp<srl>;
@@ -682,6 +683,12 @@ multiclass BFEPattern <Instruction UBFE, Instruction SBFE, Instruction MOV> {
(UBFE $src, $rshift, (MOV (i32 (IMMPopCount $mask))))
>;
+ // x & ((1 << y) - 1)
+ def : AMDGPUPat <
+ (and i32:$src, (add_oneuse (shl_oneuse 1, i32:$width), -1)),
+ (UBFE $src, (i32 0), $width)
+ >;
+
// x & (-1 >> (bitwidth - y))
def : AMDGPUPat <
(and i32:$src, (srl_oneuse -1, (sub 32, i32:$width))),
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