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| author | Sanjay Patel <spatel@rotateright.com> | 2015-01-28 18:01:31 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2015-01-28 18:01:31 +0000 |
| commit | 9bb601856e8403eaeb4b7920ee1a2c24151fe8ae (patch) | |
| tree | 2377b2d06134e7ea86dff2655ac36114066632e4 /llvm/lib | |
| parent | a05b3b73a4e9434f4e5c9fd406b02af968a5daf4 (diff) | |
| download | bcm5719-llvm-9bb601856e8403eaeb4b7920ee1a2c24151fe8ae.tar.gz bcm5719-llvm-9bb601856e8403eaeb4b7920ee1a2c24151fe8ae.zip | |
use SDValue methods directly instead of getNode()->* ; NFCI
llvm-svn: 227334
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 5aa0d9d6dbb..1fd12142966 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -13198,21 +13198,21 @@ static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG) { if (Subtarget->hasFp256()) { - SDLoc dl(Op.getNode()); - SDValue Vec = Op.getNode()->getOperand(0); - SDValue SubVec = Op.getNode()->getOperand(1); - SDValue Idx = Op.getNode()->getOperand(2); - - if ((Op.getNode()->getSimpleValueType(0).is256BitVector() || - Op.getNode()->getSimpleValueType(0).is512BitVector()) && - SubVec.getNode()->getSimpleValueType(0).is128BitVector() && + SDLoc dl(Op); + SDValue Vec = Op.getOperand(0); + SDValue SubVec = Op.getOperand(1); + SDValue Idx = Op.getOperand(2); + + if ((Op.getSimpleValueType().is256BitVector() || + Op.getSimpleValueType().is512BitVector()) && + SubVec.getSimpleValueType().is128BitVector() && isa<ConstantSDNode>(Idx)) { unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl); } - if (Op.getNode()->getSimpleValueType(0).is512BitVector() && - SubVec.getNode()->getSimpleValueType(0).is256BitVector() && + if (Op.getSimpleValueType().is512BitVector() && + SubVec.getSimpleValueType().is256BitVector() && isa<ConstantSDNode>(Idx)) { unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl); |
