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authorDiana Picus <diana.picus@linaro.org>2017-02-16 11:25:09 +0000
committerDiana Picus <diana.picus@linaro.org>2017-02-16 11:25:09 +0000
commit9b32faa8214df44c79b318b72969cd52aea69d33 (patch)
treebfedee81d29e71a6ad82b38ebd817bc8c6f25a01 /llvm/lib
parent9d98a316c5c3bc182e0c1301513c276c96b0563a (diff)
downloadbcm5719-llvm-9b32faa8214df44c79b318b72969cd52aea69d33.tar.gz
bcm5719-llvm-9b32faa8214df44c79b318b72969cd52aea69d33.zip
[ARM] GlobalISel: Assert that we don't use the FPR bank if we don't have VFP
llvm-svn: 295308
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
index 193a85502e6..f15a8b6cfcc 100644
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -13,6 +13,7 @@
#include "ARMRegisterBankInfo.h"
#include "ARMInstrInfo.h" // For the register classes
+#include "ARMSubtarget.h"
#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -173,6 +174,17 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
return InstructionMapping{};
}
+#ifndef NDEBUG
+ for (unsigned i = 0; i < NumOperands; i++) {
+ for (const auto &Mapping : OperandsMapping[i]) {
+ assert(
+ (Mapping.RegBank->getID() != ARM::FPRRegBankID ||
+ MF.getSubtarget<ARMSubtarget>().hasVFP2()) &&
+ "Trying to use floating point register bank on target without vfp");
+ }
+ }
+#endif
+
return InstructionMapping{DefaultMappingID, /*Cost=*/1, OperandsMapping,
NumOperands};
}
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