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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-24 06:59:24 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-07-24 06:59:24 +0000 |
| commit | 9acb9781050ed5e9b7f3a0fa87a49e2770c522d9 (patch) | |
| tree | c65d1653bf0e0ffab1aa7bca07cfec8f0aa0f7ba /llvm/lib | |
| parent | 0daeb63f036c48b20c7149d877b72381cc08fd4d (diff) | |
| download | bcm5719-llvm-9acb9781050ed5e9b7f3a0fa87a49e2770c522d9.tar.gz bcm5719-llvm-9acb9781050ed5e9b7f3a0fa87a49e2770c522d9.zip | |
R600: Match rcp node on pre-SI
llvm-svn: 213844
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/CaymanInstructions.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/EvergreenInstructions.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/R600Instructions.td | 7 |
3 files changed, 9 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/CaymanInstructions.td b/llvm/lib/Target/R600/CaymanInstructions.td index 26303452c10..58b5ce24b4a 100644 --- a/llvm/lib/Target/R600/CaymanInstructions.td +++ b/llvm/lib/Target/R600/CaymanInstructions.td @@ -46,6 +46,8 @@ def SIN_cm : SIN_Common<0x8D>; def COS_cm : COS_Common<0x8E>; } // End isVector = 1 +defm : RsqPat<RECIPSQRT_IEEE_cm, f32>; + def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>; defm DIV_cm : DIV_Common<RECIP_IEEE_cm>; diff --git a/llvm/lib/Target/R600/EvergreenInstructions.td b/llvm/lib/Target/R600/EvergreenInstructions.td index 484e52250d1..17edf15ed8f 100644 --- a/llvm/lib/Target/R600/EvergreenInstructions.td +++ b/llvm/lib/Target/R600/EvergreenInstructions.td @@ -69,6 +69,7 @@ def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; +defm : RsqPat<RECIPSQRT_IEEE_eg, f32>; def SIN_eg : SIN_Common<0x8D>; def COS_eg : COS_Common<0x8E>; diff --git a/llvm/lib/Target/R600/R600Instructions.td b/llvm/lib/Target/R600/R600Instructions.td index 704507d368e..436b0956f21 100644 --- a/llvm/lib/Target/R600/R600Instructions.td +++ b/llvm/lib/Target/R600/R600Instructions.td @@ -1068,7 +1068,7 @@ class RECIP_CLAMPED_Common <bits<11> inst> : R600_1OP < } class RECIP_IEEE_Common <bits<11> inst> : R600_1OP < - inst, "RECIP_IEEE", [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] + inst, "RECIP_IEEE", [(set f32:$dst, (AMDGPUrcp f32:$src0))] > { let Itinerary = TransALU; } @@ -1114,6 +1114,7 @@ def FNEG_R600 : FNEG<R600_Reg32>; // Helper patterns for complex intrinsics //===----------------------------------------------------------------------===// +// FIXME: Should be predicated on unsafe fp math. multiclass DIV_Common <InstR600 recip_ieee> { def : Pat< (int_AMDGPU_div f32:$src0, f32:$src1), @@ -1124,6 +1125,8 @@ def : Pat< (fdiv f32:$src0, f32:$src1), (MUL_IEEE $src0, (recip_ieee $src1)) >; + +def : RcpPat<recip_ieee, f32>; } class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ieee> @@ -1180,6 +1183,8 @@ let Predicates = [isR600] in { def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common<MUL_LIT_r600, LOG_CLAMPED_r600, EXP_IEEE_r600>; def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>; + defm : RsqPat<RECIPSQRT_IEEE_r600, f32>; + def : FROUNDPat <CNDGE_r600>; def R600_ExportSwz : ExportSwzInst { |
