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| author | Haicheng Wu <haicheng@codeaurora.org> | 2016-12-22 01:39:24 +0000 |
|---|---|---|
| committer | Haicheng Wu <haicheng@codeaurora.org> | 2016-12-22 01:39:24 +0000 |
| commit | 9ac20a1e1073cf8eb40d8efe42e17bd3b2be4682 (patch) | |
| tree | 7740039d393a60d4a9f4422ed17c5f98df12fc42 /llvm/lib | |
| parent | 180bd9f6b30a1cbea5adbe65d03af95148872740 (diff) | |
| download | bcm5719-llvm-9ac20a1e1073cf8eb40d8efe42e17bd3b2be4682.tar.gz bcm5719-llvm-9ac20a1e1073cf8eb40d8efe42e17bd3b2be4682.zip | |
[AArch64] Correct the check of signed 9-bit imm in getIndexedAddressParts().
-256 is a legal indexed address part.
Differential Revision: https://reviews.llvm.org/D27537
llvm-svn: 290296
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index c8200c23d49..4c98253878e 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -10272,8 +10272,10 @@ bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base, // All of the indexed addressing mode instructions take a signed // 9 bit immediate offset. if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { - int64_t RHSC = (int64_t)RHS->getZExtValue(); - if (RHSC >= 256 || RHSC <= -256) + int64_t RHSC = RHS->getSExtValue(); + if (Op->getOpcode() == ISD::SUB) + RHSC = -(uint64_t)RHSC; + if (!isInt<9>(RHSC)) return false; IsInc = (Op->getOpcode() == ISD::ADD); Offset = Op->getOperand(1); |
