[ARM GlobalISel] Support exts and truncs for Thumb2

Mark G_SEXT, G_ZEXT and G_ANYEXT to 32 bits as legal and add support for
them in the instruction selector. This uses handwritten code again
because the patterns that are generated with TableGen are tuned for what
the DAG combiner would produce and not for simple sext/zext nodes.
Luckily, we only need to update the opcodes to use the Thumb2 variants,
everything else can be reused from ARM.

llvm-svn: 349026

2 files changed, 18 insertions, 15 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index 2d5c990ab0e..4007e9e02bc 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -229,17 +229,19 @@ static bool selectUnmergeValues(MachineInstrBuilder &MIB,
 /// instruction). Extension operations more complicated than that should not
 /// invoke this. Returns the original opcode if it doesn't know how to select a
 /// better one.
-static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) {
+static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size, bool isThumb) {
   using namespace TargetOpcode;
 
   if (Size != 8 && Size != 16)
     return Opc;
 
   if (Opc == G_SEXT)
-    return Size == 8 ? ARM::SXTB : ARM::SXTH;
+    return isThumb ? Size == 8 ? ARM::t2SXTB : ARM::t2SXTH
+                   : Size == 8 ? ARM::SXTB : ARM::SXTH;
 
   if (Opc == G_ZEXT)
-    return Size == 8 ? ARM::UXTB : ARM::UXTH;
+    return isThumb ? Size == 8 ? ARM::t2UXTB : ARM::t2UXTH
+                   : Size == 8 ? ARM::UXTB : ARM::UXTH;
 
   return Opc;
 }
@@ -715,7 +717,7 @@ bool ARMInstructionSelector::select(MachineInstr &I,
     switch (SrcSize) {
     case 1: {
       // ZExt boils down to & 0x1; for SExt we also subtract that from 0
-      I.setDesc(TII.get(ARM::ANDri));
+      I.setDesc(TII.get(STI.isThumb() ? ARM::t2ANDri : ARM::ANDri));
       MIB.addImm(1).add(predOps(ARMCC::AL)).add(condCodeOp());
 
       if (isSExt) {
@@ -726,13 +728,13 @@ bool ARMInstructionSelector::select(MachineInstr &I,
         I.getOperand(0).setReg(AndResult);
 
         auto InsertBefore = std::next(I.getIterator());
-        auto SubI =
-            BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::RSBri))
-                .addDef(SExtResult)
-                .addUse(AndResult)
-                .addImm(0)
-                .add(predOps(ARMCC::AL))
-                .add(condCodeOp());
+        auto SubI = BuildMI(MBB, InsertBefore, I.getDebugLoc(),
+                            TII.get(STI.isThumb() ? ARM::t2RSBri : ARM::RSBri))
+                        .addDef(SExtResult)
+                        .addUse(AndResult)
+                        .addImm(0)
+                        .add(predOps(ARMCC::AL))
+                        .add(condCodeOp());
         if (!constrainSelectedInstRegOperands(*SubI, TII, TRI, RBI))
           return false;
       }
@@ -740,7 +742,8 @@ bool ARMInstructionSelector::select(MachineInstr &I,
     }
     case 8:
     case 16: {
-      unsigned NewOpc = selectSimpleExtOpc(I.getOpcode(), SrcSize);
+      unsigned NewOpc =
+          selectSimpleExtOpc(I.getOpcode(), SrcSize, STI.isThumb());
       if (NewOpc == I.getOpcode())
         return false;
       I.setDesc(TII.get(NewOpc));
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index 2edeeacb6c6..a8bfd03a1f4 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -82,6 +82,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
     return;
   }
 
+  getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
+      .legalForCartesianProduct({s32}, {s1, s8, s16});
+
   // We're keeping these builders around because we'll want to add support for
   // floating point to them.
   auto &LoadStoreBuilder =
@@ -126,9 +129,6 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
       setAction({Op, s32}, Libcall);
   }
 
-  getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
-      .legalForCartesianProduct({s32}, {s1, s8, s16});
-
   getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
   getActionDefinitionsBuilder(G_PTRTOINT).legalFor({{s32, p0}});