diff options
| author | Craig Topper <craig.topper@gmail.com> | 2016-04-21 06:39:26 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2016-04-21 06:39:26 +0000 |
| commit | 98c855d480225cb2aaecf9ef6d7db0179adfdc49 (patch) | |
| tree | 5bbb74d8fac8fddb18acc7297cbe0b1f76525bfc /llvm/lib | |
| parent | f95f77adf6201f5d4c708feb84fb88ee28f0d734 (diff) | |
| download | bcm5719-llvm-98c855d480225cb2aaecf9ef6d7db0179adfdc49.tar.gz bcm5719-llvm-98c855d480225cb2aaecf9ef6d7db0179adfdc49.zip | |
[X86] Remove old leftover MMX code that sets various 64-bit vector operations to Expand. These vector types aren't legal so these operations would never make it far enough to need to expand. NFC
llvm-svn: 266960
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0019b50f4b3..546a4a8a18d 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -733,23 +733,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, // No operations on x86mmx supported, everything uses intrinsics. } - // MMX-sized vectors (other than x86mmx) are expected to be expanded - // into smaller operations. - for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) { - setOperationAction(ISD::LOAD, MMXTy, Expand); - setOperationAction(ISD::SRL, MMXTy, Expand); - setOperationAction(ISD::SHL, MMXTy, Expand); - setOperationAction(ISD::SRA, MMXTy, Expand); - setOperationAction(ISD::MULHS, MMXTy, Expand); - setOperationAction(ISD::AND, MMXTy, Expand); - setOperationAction(ISD::OR, MMXTy, Expand); - setOperationAction(ISD::XOR, MMXTy, Expand); - setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand); - setOperationAction(ISD::SELECT, MMXTy, Expand); - setOperationAction(ISD::BITCAST, MMXTy, Expand); - } - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); - if (!Subtarget.useSoftFloat() && Subtarget.hasSSE1()) { addRegisterClass(MVT::v4f32, &X86::VR128RegClass); |

