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| author | Craig Topper <craig.topper@intel.com> | 2019-09-08 19:24:42 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-09-08 19:24:42 +0000 |
| commit | 97d41b8917438cb391d3c2c6fc7f5f9a01ff713a (patch) | |
| tree | 3b077de9614807bd7b1e18f2ea2f5fdb32e961c0 /llvm/lib | |
| parent | dac34f52d3f94b4b8716ee8f2cc0c086161d326d (diff) | |
| download | bcm5719-llvm-97d41b8917438cb391d3c2c6fc7f5f9a01ff713a.tar.gz bcm5719-llvm-97d41b8917438cb391d3c2c6fc7f5f9a01ff713a.zip | |
[X86] Use DAG.getConstant instead of getZeroVector in combinePMULDQ.
getZeroVector canonicalizes the type to vXi32, but that's a
legalization action. We should use the most correct type if
possible.
llvm-svn: 371345
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index c7844220dfc..3950b292ab3 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -44768,7 +44768,7 @@ static SDValue combinePMULDQ(SDNode *N, SelectionDAG &DAG, // Multiply by zero. // Don't return RHS as it may contain UNDEFs. if (ISD::isBuildVectorAllZeros(RHS.getNode())) - return getZeroVector(N->getSimpleValueType(0), Subtarget, DAG, SDLoc(N)); + return DAG.getConstant(0, SDLoc(N), N->getValueType(0)); // PMULDQ/PMULUDQ only uses lower 32 bits from each vector element. const TargetLowering &TLI = DAG.getTargetLoweringInfo(); |
