diff options
author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-30 19:49:48 +0000 |
---|---|---|
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-09-30 19:49:48 +0000 |
commit | 9706978077b99d0da8273b7499af4d50812defae (patch) | |
tree | bbdf4eb8268a9198b8733680dabbac6276101492 /llvm/lib | |
parent | 272c50a1fec048bcbe59c80c6065f5a9623b3fa1 (diff) | |
download | bcm5719-llvm-9706978077b99d0da8273b7499af4d50812defae.tar.gz bcm5719-llvm-9706978077b99d0da8273b7499af4d50812defae.zip |
R600/SI: Fix printing of clamp and omod
No tests for omod since nothing uses it yet, but
this should get rid of the remaining annoying trailing
zeros after some instructions.
llvm-svn: 218692
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp | 17 | ||||
-rw-r--r-- | llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h | 2 | ||||
-rw-r--r-- | llvm/lib/Target/R600/SIDefines.h | 9 | ||||
-rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.td | 44 |
4 files changed, 55 insertions, 17 deletions
diff --git a/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp b/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp index 9bb8beca7bb..3a2055678dd 100644 --- a/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp @@ -294,6 +294,23 @@ void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo, printIfSet(MI, OpNo, O, "_SAT"); } +void AMDGPUInstPrinter::printClampSI(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + if (MI->getOperand(OpNo).getImm()) + O << " clamp"; +} + +void AMDGPUInstPrinter::printOModSI(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + int Imm = MI->getOperand(OpNo).getImm(); + if (Imm == SIOutMods::MUL2) + O << " mul:2"; + else if (Imm == SIOutMods::MUL4) + O << " mul:4"; + else if (Imm == SIOutMods::DIV2) + O << " div:2"; +} + void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O) { int32_t Imm = MI->getOperand(OpNo).getImm(); diff --git a/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h b/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h index 83f42a18a46..6954dafe7c3 100644 --- a/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h @@ -52,6 +52,8 @@ private: StringRef Asm, StringRef Default = ""); static void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O); static void printClamp(const MCInst *MI, unsigned OpNo, raw_ostream &O); + static void printClampSI(const MCInst *MI, unsigned OpNo, raw_ostream &O); + static void printOModSI(const MCInst *MI, unsigned OpNo, raw_ostream &O); static void printLiteral(const MCInst *MI, unsigned OpNo, raw_ostream &O); static void printLast(const MCInst *MI, unsigned OpNo, raw_ostream &O); static void printNeg(const MCInst *MI, unsigned OpNo, raw_ostream &O); diff --git a/llvm/lib/Target/R600/SIDefines.h b/llvm/lib/Target/R600/SIDefines.h index 29be2e67169..2e7dab6cb56 100644 --- a/llvm/lib/Target/R600/SIDefines.h +++ b/llvm/lib/Target/R600/SIDefines.h @@ -43,6 +43,15 @@ namespace SISrcMods { }; } +namespace SIOutMods { + enum { + NONE = 0, + MUL2 = 1, + MUL4 = 2, + DIV2 = 3 + }; +} + #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td index f2c13079325..6b7da98e4bc 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.td +++ b/llvm/lib/Target/R600/SIInstrInfo.td @@ -185,6 +185,14 @@ def tfe : Operand <i1> { let PrintMethod = "printTFE"; } +def omod : Operand <i32> { + let PrintMethod = "printOModSI"; +} + +def ClampMod : Operand <i1> { + let PrintMethod = "printClampSI"; +} + } // End OperandType = "OPERAND_IMMEDIATE" //===----------------------------------------------------------------------===// @@ -399,7 +407,7 @@ class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC, !if (!eq(HasModifiers, 1), // VOP1 with modifiers (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, - i32imm:$clamp, i32imm:$omod) + ClampMod:$clamp, omod:$omod) /* else */, // VOP1 without modifiers (ins Src0RC:$src0) @@ -409,7 +417,7 @@ class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC, // VOP 2 with modifiers (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, InputModsNoDefault:$src1_modifiers, Src1RC:$src1, - i32imm:$clamp, i32imm:$omod) + ClampMod:$clamp, omod:$omod) /* else */, // VOP2 without modifiers (ins Src0RC:$src0, Src1RC:$src1) @@ -420,7 +428,7 @@ class getIns64 <RegisterClass Src0RC, RegisterClass Src1RC, (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, InputModsNoDefault:$src1_modifiers, Src1RC:$src1, InputModsNoDefault:$src2_modifiers, Src2RC:$src2, - i32imm:$clamp, i32imm:$omod) + ClampMod:$clamp, omod:$omod) /* else */, // VOP3 without modifiers (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2) @@ -442,12 +450,14 @@ class getAsm32 <int NumSrcArgs> { // instruction. class getAsm64 <int NumSrcArgs, bit HasModifiers> { string src0 = "$src0_modifiers,"; - string src1 = !if(!eq(NumSrcArgs, 1), "", " $src1_modifiers,"); - string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers,", ""); + string src1 = !if(!eq(NumSrcArgs, 1), "", + !if(!eq(NumSrcArgs, 2), " $src1_modifiers", + " $src1_modifiers,")); + string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", ""); string ret = !if(!eq(HasModifiers, 0), getAsm32<NumSrcArgs>.ret, - " $dst, "#src0#src1#src2#" $clamp, $omod"); + " $dst, "#src0#src1#src2#"$clamp"#"$omod"); } @@ -632,7 +642,7 @@ multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P, P.Ins64, P.Asm64, !if(P.HasModifiers, [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, - i32:$src0_modifiers, i32:$clamp, i32:$omod))))], + i32:$src0_modifiers, i1:$clamp, i32:$omod))))], [(set P.DstVT:$dst, (node P.Src0VT:$src0))]), P.HasModifiers >; @@ -664,7 +674,7 @@ multiclass VOP2Inst <bits<6> op, string opName, VOPProfile P, !if(P.HasModifiers, [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, - i32:$clamp, i32:$omod)), + i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), revOp, P.HasModifiers @@ -692,7 +702,7 @@ multiclass VOP2bInst <bits<6> op, string opName, VOPProfile P, !if(P.HasModifiers, [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, - i32:$clamp, i32:$omod)), + i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), revOp, P.HasModifiers @@ -719,7 +729,7 @@ multiclass VOPCInst <bits<8> op, string opName, !if(P.HasModifiers, [(set i1:$dst, (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, - i32:$clamp, i32:$omod)), + i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), cond))], [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]), @@ -767,7 +777,7 @@ multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P, !if(P.HasModifiers, [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, - i32:$clamp, i32:$omod)), + i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))], [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1, @@ -776,14 +786,14 @@ multiclass VOP3Inst <bits<9> op, string opName, VOPProfile P, !if(P.HasModifiers, [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, - i32:$clamp, i32:$omod)), + i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]) /* P.NumSrcArgs == 1 */, !if(P.HasModifiers, [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, - i32:$clamp, i32:$omod))))], + i1:$clamp, i32:$omod))))], [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))), P.NumSrcArgs, P.HasModifiers >; @@ -795,8 +805,8 @@ multiclass VOP3b_Helper <bits<9> op, RegisterClass vrc, RegisterClass arc, (ins InputModsNoDefault:$src0_modifiers, arc:$src0, InputModsNoDefault:$src1_modifiers, arc:$src1, InputModsNoDefault:$src2_modifiers, arc:$src2, - i32imm:$clamp, i32imm:$omod), - opName#" $dst0, $dst1, $src0_modifiers, $src1_modifiers, $src2_modifiers, $clamp, $omod", pattern, + ClampMod:$clamp, i32imm:$omod), + opName#" $dst0, $dst1, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", pattern, opName, opName, 1, 1 >; @@ -808,13 +818,13 @@ multiclass VOP3b_32 <bits<9> op, string opName, list<dag> pattern> : class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat< - (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i32:$clamp, i32:$omod)), + (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))), (Inst i32:$src0_modifiers, P.Src0VT:$src0, i32:$src1_modifiers, P.Src1VT:$src1, i32:$src2_modifiers, P.Src2VT:$src2, - i32:$clamp, + i1:$clamp, i32:$omod)>; //===----------------------------------------------------------------------===// |