add support for the "r" asm constraint

patch by Lauro Ramos Venancio

llvm-svn: 32224

1 files changed, 27 insertions, 0 deletions

diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index a7e4703a665..7f5e35a9937 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -18,6 +18,7 @@
 #include "llvm/Function.h"
 #include "llvm/Constants.h"
 #include "llvm/Intrinsics.h"
+#include "llvm/ADT/VectorExtras.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -37,6 +38,9 @@ namespace {
     ARMTargetLowering(TargetMachine &TM);
     virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
     virtual const char *getTargetNodeName(unsigned Opcode) const;
+    std::vector<unsigned>
+    getRegClassForInlineAsmConstraint(const std::string &Constraint,
+				      MVT::ValueType VT) const;
   };
 
 }
@@ -200,6 +204,29 @@ static ARMCC::CondCodes DAGIntCCToARMCC(ISD::CondCode CC) {
   }
 }
 
+std::vector<unsigned> ARMTargetLowering::
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+                                  MVT::ValueType VT) const {
+  if (Constraint.size() == 1) {
+    // FIXME: handling only r regs
+    switch (Constraint[0]) {
+    default: break;  // Unknown constraint letter
+
+    case 'r':   // GENERAL_REGS
+    case 'R':   // LEGACY_REGS
+      if (VT == MVT::i32)
+        return make_vector<unsigned>(ARM::R0,  ARM::R1,  ARM::R2,  ARM::R3,
+                                     ARM::R4,  ARM::R5,  ARM::R6,  ARM::R7,
+                                     ARM::R8,  ARM::R9,  ARM::R10, ARM::R11,
+                                     ARM::R12, ARM::R13, ARM::R14, 0);
+      break;
+
+    }
+  }
+
+  return std::vector<unsigned>();
+}
+
 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch (Opcode) {
   default: return 0;