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| author | Sam Parker <sam.parker@arm.com> | 2017-08-18 08:39:54 +0000 |
|---|---|---|
| committer | Sam Parker <sam.parker@arm.com> | 2017-08-18 08:39:54 +0000 |
| commit | 96f8959cfd0b1b12d4252b4d7523d35a49ea1cea (patch) | |
| tree | 7d38aff65c2a250172d51f89c092be885e9bf20d /llvm/lib | |
| parent | f698a29a513566be1ae7f67be2afd4574999c9c2 (diff) | |
| download | bcm5719-llvm-96f8959cfd0b1b12d4252b4d7523d35a49ea1cea.tar.gz bcm5719-llvm-96f8959cfd0b1b12d4252b4d7523d35a49ea1cea.zip | |
[AArch64] Remove DecodeAuthLoadWriteback
The BaseAuthLoad instruction class was incorrectly passing an empty
constraint string to its parent, so I have corrected this. This makes
the DecodeAuthLoadWriteback function redundant, so I've also removed
it.
Differential Revision: https://reviews.llvm.org/D36741
llvm-svn: 311148
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstrFormats.td | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 21 |
2 files changed, 4 insertions, 26 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td index 49c52c2f5ef..2e8c56a2b50 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -1169,7 +1169,7 @@ class AuthReturn<bits<3> op, bits<1> M, string asm> let mayLoad = 1 in class BaseAuthLoad<bit M, bit W, dag oops, dag iops, string asm, string operands, string cstr, Operand opr> - : I<oops, iops, asm, operands, "", []>, Sched<[]> { + : I<oops, iops, asm, operands, cstr, []>, Sched<[]> { bits<10> offset; bits<5> Rn; bits<5> Rt; @@ -1185,14 +1185,13 @@ class BaseAuthLoad<bit M, bit W, dag oops, dag iops, string asm, } multiclass AuthLoad<bit M, string asm, Operand opr> { - def indexed : BaseAuthLoad<M, 0, (outs GPR64:$Rt), (ins GPR64sp:$Rn, opr:$offset), + def indexed : BaseAuthLoad<M, 0, (outs GPR64:$Rt), + (ins GPR64sp:$Rn, opr:$offset), asm, "\t$Rt, [$Rn, $offset]", "", opr>; def writeback : BaseAuthLoad<M, 1, (outs GPR64sp:$wback, GPR64:$Rt), (ins GPR64sp:$Rn, opr:$offset), asm, "\t$Rt, [$Rn, $offset]!", - "$Rn = $wback,@earlyclobber $wback", opr> { - let DecoderMethod = "DecodeAuthLoadWriteback"; - } + "$Rn = $wback,@earlyclobber $wback", opr>; def : InstAlias<asm # "\t$Rt, [$Rn]", (!cast<Instruction>(NAME # "indexed") GPR64:$Rt, GPR64sp:$Rn, 0)>; diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 4389df7fa53..36b48d5aace 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -1609,24 +1609,3 @@ static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, return Success; } -static DecodeStatus DecodeAuthLoadWriteback(llvm::MCInst &Inst, uint32_t insn, - uint64_t Address, - const void *Decoder) { - unsigned Rt = fieldFromInstruction(insn, 0, 5); - unsigned Rn = fieldFromInstruction(insn, 5, 5); - unsigned Imm9 = fieldFromInstruction(insn, 12, 9); - unsigned S = fieldFromInstruction(insn, 22, 1); - - unsigned Imm = Imm9 | (S << 9); - - // Address writeback - DecodeGPR64spRegisterClass(Inst, Rn, Address, Decoder); - // Destination - DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); - // Address - DecodeGPR64spRegisterClass(Inst, Rn, Address, Decoder); - // Offset - DecodeSImm<10>(Inst, Imm, Address, Decoder); - - return Success; -} |

