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| author | Simon Dardis <simon.dardis@imgtec.com> | 2017-10-10 14:41:11 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2017-10-10 14:41:11 +0000 |
| commit | 96d35fe06add34594f4b0e7960122a58445ee3e0 (patch) | |
| tree | 7c1649f54cab29838923fe7a398fd8b82463d602 /llvm/lib | |
| parent | 3847be551469fe3715961747dd9637a2cbf5f7b9 (diff) | |
| download | bcm5719-llvm-96d35fe06add34594f4b0e7960122a58445ee3e0.tar.gz bcm5719-llvm-96d35fe06add34594f4b0e7960122a58445ee3e0.zip | |
[mips] Duplicate the reciprocal instruction definitions for FP32
Add instruction definitions for FP32 mode for recip.d and rsqrt.d.
Previously these instructions were only defined when targeting the
full 64-bit FPU model but were not guarded properly.
Reviewers: nitesh.jain, atanasyan
Differential Revision: https://reviews.llvm.org/D38400
llvm-svn: 315318
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MicroMipsInstrFPU.td | 24 | ||||
| -rw-r--r-- | llvm/lib/Target/Mips/MipsInstrFPU.td | 20 |
2 files changed, 34 insertions, 10 deletions
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td index 2fbe930c37b..29ef471788a 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td @@ -169,16 +169,28 @@ let AdditionalPredicates = [InMicroMips] in { def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, ROUND_W_FM_MM<0b0, 0b01001000>; - def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, - II_RECIP_D>, - ROUND_W_FM_MM<0b1, 0b01001000>; + def RECIP_D32_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, + II_RECIP_D>, + ROUND_W_FM_MM<0b1, 0b01001000>, FGR_32 { + let BaseOpcode = "RECIP_D32"; + } + let DecoderNamespace = "MicroMipsFP64" in + def RECIP_D64_MM : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, + II_RECIP_D>, + ROUND_W_FM_MM<0b1, 0b01001000>, FGR_64; def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, ROUND_W_FM_MM<0b0, 0b00001000>; - def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, + def RSQRT_D32_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>, - ROUND_W_FM_MM<0b1, 0b00001000>; - } + ROUND_W_FM_MM<0b1, 0b00001000>, FGR_32 { + let BaseOpcode = "RSQRT_D32"; + } + let DecoderNamespace = "MicroMipsFP64" in + def RSQRT_D64_MM : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, + II_RECIP_D>, + ROUND_W_FM_MM<0b1, 0b00001000>, FGR_64; + } let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in { def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>, LW_FM_MM<0x2f>, FGR_32 { diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index c2338f2d901..75e1b2be2a4 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -369,12 +369,24 @@ defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; let AdditionalPredicates = [NotInMicroMips] in { def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2; - def RECIP_D : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, II_RECIP_D>, - ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2; + def RECIP_D32 : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, II_RECIP_D>, + ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2, FGR_32 { + let BaseOpcode = "RECIP_D32"; + } + let DecoderNamespace = "MipsFP64" in + def RECIP_D64 : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, + II_RECIP_D>, ABSS_FM<0b010101, 0x11>, + INSN_MIPS4_32R2, FGR_64; def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>, ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2; - def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>, - ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2; + def RSQRT_D32 : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, II_RSQRT_D>, + ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2, FGR_32 { + let BaseOpcode = "RSQRT_D32"; + } + let DecoderNamespace = "MipsFP64" in + def RSQRT_D64 : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, + II_RSQRT_D>, ABSS_FM<0b010110, 0x11>, + INSN_MIPS4_32R2, FGR_64; } let DecoderNamespace = "MipsFP64" in { let AdditionalPredicates = [NotInMicroMips] in { |
