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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-02-17 19:07:59 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-02-17 19:07:59 +0000 |
| commit | 96732a438dc8de4cf619402d82e63e725575b47e (patch) | |
| tree | 74c04336b8f0a4e248e3c4eb5d0f3b388216d577 /llvm/lib | |
| parent | a0cf42f2e1bc8534258f6a72e718e78214e00e9f (diff) | |
| download | bcm5719-llvm-96732a438dc8de4cf619402d82e63e725575b47e.tar.gz bcm5719-llvm-96732a438dc8de4cf619402d82e63e725575b47e.zip | |
Fix ARMBaseInstrInfo::getInstrLatency for calls.
Calls always clobber CPSR.
llvm-svn: 150831
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 2d7df09411d..166b248f913 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -2849,7 +2849,7 @@ int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, const MCInstrDesc &MCID = MI->getDesc(); unsigned Class = MCID.getSchedClass(); unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; - if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) + if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) // When predicated, CPSR is an additional source operand for CPSR updating // instructions, this apparently increases their latencies. *PredCost = 1; |
