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authorCraig Topper <craig.topper@intel.com>2018-12-02 19:47:14 +0000
committerCraig Topper <craig.topper@intel.com>2018-12-02 19:47:14 +0000
commit959b415e2fcbc3457ad00baa8c727ab16e6e1cbf (patch)
treed9ad48240c4ef576b914b46a5a30ed081294fe09 /llvm/lib
parent6f54ff57fd99e366fd937316777757b8541920df (diff)
downloadbcm5719-llvm-959b415e2fcbc3457ad00baa8c727ab16e6e1cbf.tar.gz
bcm5719-llvm-959b415e2fcbc3457ad00baa8c727ab16e6e1cbf.zip
[X86] Add a DAG combine to turn stores of vXi1 on pre-avx512 targets into a bitcast and a store of a iX scalar.
llvm-svn: 348104
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 43e84b396e6..fdf7d1b41f4 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -37296,6 +37296,18 @@ static SDValue combineStore(SDNode *N, SelectionDAG &DAG,
SDValue StoredVal = St->getOperand(1);
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+ // Convert a store of vXi1 into a store of iX and a bitcast.
+ if (!Subtarget.hasAVX512() && VT == StVT && VT.isVector() &&
+ VT.getVectorElementType() == MVT::i1) {
+
+ EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), VT.getVectorNumElements());
+ StoredVal = DAG.getBitcast(NewVT, StoredVal);
+
+ return DAG.getStore(St->getChain(), dl, StoredVal, St->getBasePtr(),
+ St->getPointerInfo(), St->getAlignment(),
+ St->getMemOperand()->getFlags());
+ }
+
// If this is a store of a scalar_to_vector to v1i1, just use a scalar store.
// This will avoid a copy to k-register.
if (VT == MVT::v1i1 && VT == StVT && Subtarget.hasAVX512() &&
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