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| author | Craig Topper <craig.topper@intel.com> | 2019-10-14 23:48:24 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-10-14 23:48:24 +0000 |
| commit | 9586d85ab3badcf8ca2292ca6019caea4e6513c4 (patch) | |
| tree | 4fc60d0069ef5f49a56bccf05eddd9e4e748e6f3 /llvm/lib | |
| parent | 5e80715508d1b819f99f574c869805e5e3aecb11 (diff) | |
| download | bcm5719-llvm-9586d85ab3badcf8ca2292ca6019caea4e6513c4.tar.gz bcm5719-llvm-9586d85ab3badcf8ca2292ca6019caea4e6513c4.zip | |
[X86] Teach X86MCodeEmitter to properly encode zmm16-zmm31 as index register to vgatherpf/vscatterpf.
We need to encode bit 4 into the EVEX.V' bit. We do this right
for regular gather/scatter which use either MRMSrcMem or MRMDestMem
formats. The prefetches use MRM*m formats.
Fixes an issue recently added to PR36202.
llvm-svn: 374849
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 31d26d08a63..ac36bf3a12f 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -862,6 +862,9 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, VEX_B = ~(BaseRegEnc >> 3) & 1; unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); VEX_X = ~(IndexRegEnc >> 3) & 1; + if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV. + EVEX_V2 = ~(IndexRegEnc >> 4) & 1; + break; } case X86II::MRMSrcReg: { |
