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| author | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-22 15:53:50 +0000 |
|---|---|---|
| committer | Tim Renouf <tpr.llvm@botech.co.uk> | 2019-03-22 15:53:50 +0000 |
| commit | 94c163c34e4d1d9f2fd7887f198a6fac3c71e271 (patch) | |
| tree | 5e01a80f5df9d56ed107568cbac8f90e60da0173 /llvm/lib | |
| parent | 056a8ba48378a0704bb873d2f49cbff8ba4a28e3 (diff) | |
| download | bcm5719-llvm-94c163c34e4d1d9f2fd7887f198a6fac3c71e271.tar.gz bcm5719-llvm-94c163c34e4d1d9f2fd7887f198a6fac3c71e271.zip | |
InstCombineSimplifyDemanded: Allow v3 results for AMDGCN buffer and image intrinsics
This helps to avoid the situation where RA spots that only 3 of the
v4f32 result of a load are used, and immediately reallocates the 4th
register for something else, requiring a stall waiting for the load.
Differential Revision: https://reviews.llvm.org/D58906
Change-Id: I947661edfd5715f62361a02b100f14aeeada29aa
llvm-svn: 356768
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index b79a4d78648..2dea7eea404 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -1003,8 +1003,7 @@ Value *InstCombiner::simplifyAMDGCNMemoryIntrinsicDemanded(IntrinsicInst *II, NewDMask = ConstantInt::get(DMask->getType(), NewDMaskVal); } - // TODO: Handle 3 vectors when supported in code gen. - unsigned NewNumElts = PowerOf2Ceil(DemandedElts.countPopulation()); + unsigned NewNumElts = DemandedElts.countPopulation(); if (!NewNumElts) return UndefValue::get(II->getType()); |
