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authorSimon Pilgrim <llvm-dev@redking.me.uk>2016-11-29 13:43:08 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2016-11-29 13:43:08 +0000
commit923020a6520e23595802441f12d16888ae7f8947 (patch)
tree653e03fc36fcc3230665c0fea0d8c3810efc740e /llvm/lib
parent160bf723f597ddb5e86ad3f76e65a957c1d06e66 (diff)
downloadbcm5719-llvm-923020a6520e23595802441f12d16888ae7f8947.tar.gz
bcm5719-llvm-923020a6520e23595802441f12d16888ae7f8947.zip
Avoid repeated calls to MVT::getScalarSizeInBits(). NFCI.
llvm-svn: 288138
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index bb6faab3a19..02e06572422 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -25447,12 +25447,12 @@ static bool matchUnaryVectorShuffle(MVT MaskVT, ArrayRef<int> Mask,
const X86Subtarget &Subtarget,
unsigned &Shuffle, MVT &ShuffleVT) {
unsigned NumMaskElts = Mask.size();
+ unsigned MaskEltSize = MaskVT.getScalarSizeInBits();
bool FloatDomain = MaskVT.isFloatingPoint() ||
(!Subtarget.hasAVX2() && MaskVT.is256BitVector());
// Match against a VZEXT_MOVL instruction, SSE1 only supports 32-bits (MOVSS).
- if (((MaskVT.getScalarSizeInBits() == 32) ||
- (MaskVT.getScalarSizeInBits() == 64 && Subtarget.hasSSE2())) &&
+ if (((MaskEltSize == 32) || (MaskEltSize == 64 && Subtarget.hasSSE2())) &&
isUndefOrEqual(Mask[0], 0) &&
isUndefOrZeroInRange(Mask, 1, NumMaskElts - 1)) {
Shuffle = X86ISD::VZEXT_MOVL;
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